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74ALVCH16601 반도체 회로 부품 판매점

18-bit universal bus transceiver 3-State



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NXP Semiconductors
74ALVCH16601 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
74ALVCH16601
18-bit universal bus transceiver (3-State)
Product specification
Supersedes data of 1998 Aug 31
IC24 Data Handbook
1998 Sep 24
Philips
Semiconductors


74ALVCH16601 데이터시트, 핀배열, 회로
Philips Semiconductors
18-bit universal bus transceiver (3-State)
Product specification
74ALVCH16601
FEATURES
Complies with JEDEC standard no. 8-1A
CMOS low power consumption
Direct interface with TTL levels
MULTIBYTETM flow-through standard pin-out architecture
Low inductance multiple VCC and ground pins for minimum noise
and ground bounce
Current drive ± 24 mA at 3.0 V
All inputs have bus hold circuitry
Output drive capability 50transmission lines @ 85°C
DESCRIPTION
The 74ALVCH16601 is an 18-bit universal transceiver featuring
non-inverting 3-State bus compatible outputs in both send and
receive directions. Data flow in each direction is controlled by output
enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock
(CPAB and CPBA) inputs. For A-to-B data flow, the device operates
in the transparent mode when LEAB is High. When LEAB is Low, the
A data is latched if CPAB is held at a High or Low logic level. If LEAB
is Low, the A-bus data is stored in the latch/flip-flop on the
Low-to-High transition of CPAB. When OEAB is Low, the outputs are
active. When OEAB is High, the outputs are in the high-impedance
state. The clocks can be controlled with the clock-enable inputs
(CEBA/CEAB).
Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA
and CPBA.
To ensure the high impedance state during power up or power
down, OEBA and OEAB should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the
current-sinking/current-sourcing capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data
inputs at a valid logic level.
QUICK REFERENCE DATA
GND = 0V; Tamb = 25°C; tr = tf = 2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
Propagation delay
An, Bn to Bn, An
VCC = 2.5V, CL = 30pF
VCC = 3.3V, CL = 50pF
3.1 ns
2.8
CI/O Input/Output capacitance
8.0 pF
CI Input capacitance
4.0 pF
Outputs enabled
21
CPD
Power dissipation capacitance per latch
VI = GND to VCC1
Outputs disabled
3
pF
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in mW):
PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
S (CL × VCC2 × fo) = sum of outputs.
ORDERING INFORMATION
PACKAGES
56-Pin Plastic TSSOP Type II
TEMPERATURE RANGE
–40°C to +85°C
OUTSIDE NORTH AMERICA
74ALVCH16601 DGG
DWG NUMBER
SOT364-1
1998 Sep 24
2 853-2122 20076




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74ALVCH16601 transceiver

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