74ALVC16500MTD 반도체 회로 부품 판매점

Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs



Fairchild Semiconductor 로고
Fairchild Semiconductor
74ALVC16500MTD 데이터시트, 핀배열, 회로
October 2001
Revised October 2001
74ALVC16500
Low Voltage 18-Bit Universal Bus Transceivers
with 3.6V Tolerant Inputs and Outputs
General Description
The ALVC16500 is an 18-bit universal bus transceiver
which combines D-type latches and D-type flip-flops to
allow data flow in transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the
device operates in the transparent mode when LEAB is
HIGH. When LEAB is LOW, the A data is latched if CLKAB
is held at a HIGH or LOW logic level. If LEAB is LOW, the A
bus data is stored in the latch/flip-flop on the HIGH-to-LOW
transition of CLKAB. When OEAB is HIGH, the outputs are
active. When OEAB is LOW, the outputs are in a high-
impedance state.
Data flow for B to A is similar to that of A to B but uses
OEBA, LEBA, and CLKBA. The output enables are com-
plementary (OEAB is active HIGH and OEBA is active
LOW).
The ALVC16500 is designed for low voltage (1.65V to
3.6V) VCC applications with I/O capability up to 3.6V.
The 74ALVC16500 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s 1.65V–3.6V VCC supply operation
s 3.6V tolerant inputs and outputs
s tPD (A to B, B to A)
3.4 ns max for 3.0V to 3.6V VCC
4.0 ns max for 2.3V to 2.7V VCC
7.0 ns max for 1.65V to 1.95V VCC
s Power-off high impedance inputs and outputs
s Supports live insertion/withdrawal (Note 1)
s Uses patented noise/EMI reduction circuitry
s Latchup conforms to JEDEC JED78
s ESD performance:
Human body model > 2000V
Machine model >200V
Note 1: To ensure the high-impedance state during power up or power
down, OEBA should be tied to VCC through a pull-up resistor and OEAB
should be tied to GND through a pull-down resistors; the minimum value of
the resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number Package Number
Package Description
74ALVC16500MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available on Tape and Reel. Specify by appending the suffix letter Xto the ordering code.
© 2001 Fairchild Semiconductor Corporation DS500684
www.fairchildsemi.com

74ALVC16500MTD 데이터시트, 핀배열, 회로
Connection Diagram
Pin Descriptions
Pin Names
Description
OEAB
Output Enable Input for A to B Direction
(Active HIGH)
OEBA
Output Enable Input for B to A Direction
(Active LOW)
LEAB, LEBA Latch Enable Inputs
CLKAB,
CLKBA
Clock Inputs
A1A18
B1B18
Side A Inputs or 3-STATE Outputs
Side B Inputs or 3-STATE Outputs
Function Table (Note 2)
Inputs
Outputs
OEAB LEAB CLKAB An
Bn
LXXX
Z
HHX L
L
HHXH
H
HLL
L
HLH
H
H L H X B0 (Note 3)
H L L X B0 (Note 4)
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial (HIGH or LOW, inputs may not float)
Z = High Impedance
Note 2: A-to-B data flow is shown; B-to-A flow is similar but uses OEBA,
LEBA and CLKBA. OEBA is active LOW.
Note 3: Output level before the indicated steady-state input conditions
were established.
Note 4: Output level before the indicated steady-state input conditions
were established, provided that CLKAB was LOW before LEAB went LOW.
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74ALVC16500MTD transceiver

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74ALVC16500MTD

Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs - Fairchild Semiconductor