74ACTQ652 반도체 회로 부품 판매점
Quiet Series Transceiver/Register
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 Fairchild Semiconductor |
June 1991
Revised November 1999
74ACTQ652
Quiet Series Transceiver/Register
General Description
The ACTQ652 consists of bus transceiver circuits with D-
type flip-flops, and control circuitry arranged for multiplexed
transmission of data directly from the input bus or from
internal registers. Data on the A or B bus will be clocked
into the registers as the appropriate clock pin goes to the
HIGH logic level. Output Enable pins (OEAB, OEBA) are
provided to control the transceiver function.
The ACTQ652 utilizes Fairchild FACT Quiet Series tech-
nology to guarantee quiet output switching and improved
dynamic threshold performance. FACT Quiet Series fea-
tures GTO output control and undershoot corrector in
addition to split ground bus for superior performance.
Features
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed pin-to-pin skew AC performance
s Independent registers for A and B buses
s Multiplexed real-time and stored data
s Outputs source/sink 24 mA
s TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74ACTQ652SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ACTQ652MTC
MTC24
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACTQ652SPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
A0–A7, B0–B7
CPAB, CPBA
SAB, SBA
OEAB, OEBA
Description
A and B Inputs/3-STATE Outputs
Clock Inputs
Select Inputs
Output Enable Inputs
FACT, Quiet Series, FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS010933
www.fairchildsemi.com
Function Table
Inputs
OEAB OEBA CPAB CPBA
SAB
SBA
Inputs/Outputs (Note 1)
A0 thru A7
B0 thru B7
Operating Mode
L H H or L H or L X X
Isolation
L H
XX
Input
Input
Store A and B Data
X H
H or L
X
X
Input
Not Specified Store A, Hold B
H H
XX
Input
Output
Store A in Both Registers
L X H or L
X
X Not Specified
Input
Hold A, Store B
L L
XX
Output
Input
Store B in Both Registers
L LXXXL
L L X H or L X H
Output
Input
Real-Time B Data to A Bus
Store B Data to A Bus
HHXX L X
H H H or L X H X
Input
Output
Real-Time A Data to B Bus
Stored A Data to B Bus
H L H or L H or L H H
Output
Output
Stored A Data to B Bus and
Stored B Data to A Bus
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
Note 1: The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input functions are always enabled,
i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74ACTQ652 transceiver
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국내 전력반도체 판매점
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