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74ACTQ464ASPC 반도체 회로 부품 판매점

Quiet Series Octal Transceiver/Register with 3-STATE Outputs



Fairchild Semiconductor 로고
Fairchild Semiconductor
74ACTQ464ASPC 데이터시트, 핀배열, 회로
January 1990
Revised September 2000
74ACQ646 74ACTQ646
Quiet SeriesOctal Transceiver/Register
with 3-STATE Outputs
General Description
The ACQ/ACTQ646 consist of registered bus transceiver
circuits, with outputs, D-type flip-flops, and control circuitry
providing multiplexed transmission of data directly from the
input bus or from the internal storage registers. Data on the
A or B bus will be loaded into the respective registers on
the LOW-to-HIGH transition of the appropriate clock pin
(CPAB or CPBA). The four fundamental handling functions
available are illustrated in Figure 1, Figure 2, Figure 3 and
Figure 4.
The ACQ/ACTQ utilizes Fairchild Quiet Seriestechnol-
ogy to guarantee quiet output switching and improved
dynamic threshold performance. FACT Quiet Seriesfea-
tures GTOoutput control and undershoot corrector in
addition to a split ground bus for superior performance.
Features
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed pin-to-pin skew AC performance
s Independent registers for A and B busses
s Multiplexed real-time and stored data transfers
s 300 mil slim dual-in-line package
s Outputs source/sink 24 mA
s Faster prop delays than the standard AC/ACT646
Ordering Code:
Order Number Package Number
Package Description
74ACQ646SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74ACQ464ASPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74ACTQ646SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74ACTQ464ASPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
A0A7
B0B7
CPAB, CPBA
SAB, SBA
G
DIR
Descriptions
Data Register A Inputs
Data Register A Outputs
Data Register B Inputs
Data Register B Outputs
Clock Pulse Inputs
Transmit/Receive Inputs
Output Enable Input
Direction Control Input
FACT, Quiet Series, FACT Quiet Seriesand GTOare trademarks of Fairchild Semiconductor Corporation
© 2000 Fairchild Semiconductor Corporation DS010635
www.fairchildsemi.com


74ACTQ464ASPC 데이터시트, 핀배열, 회로
Logic Symbols
IEEE/IEC
Function Table
Inputs
Data I/O (Note 1)
G DIR CPAB CPBA SAB SBA A0A7 B0B7
Function
H X H or L H or L
H X
X
H X X
L H X X
LH
X
L H H or L X
LH
X
L L X X
LLX
L L X H or L
LLX
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Transition
X
X
X
L
L
H
H
X
X
X
X
X Isolation
X Input Input Clock An Data into A Register
X Clock Bn Data into B Register
X An to BnReal Time (Transparent Mode)
X Input Output Clock An Data into A Register
X A Register to Bn (Stored Mode)
X Clock An Data into A Register and Output to Bn
L Bn to AnReal Time (Transparent Mode)
L Output Input Clock Bn Data into B Register
H B Register to An (Stored Mode)
H Clock Bn Data into B Register and Output to An
Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled; i.e., data
at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs.
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74ACTQ464ASPC transceiver

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74ACTQ464ASPC

Quiet Series Octal Transceiver/Register with 3-STATE Outputs - Fairchild Semiconductor