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54ABT16245 반도체 회로 부품 판매점

16-Bit Transceiver with TRI-STATE Outputs



National Semiconductor 로고
National Semiconductor
54ABT16245 데이터시트, 핀배열, 회로
August 1998
54ABT16245
16-Bit Transceiver with TRI-STATE® Outputs
General Description
The ’ABT16245 contains sixteen non-inverting bidirectional
buffers with TRI-STATE outputs and is intended for bus ori-
ented applications. The device is byte controlled. Each byte
has separate control inputs which can be shorted together
for full 16-bit operation. The T/R inputs determine the direc-
tion of data flow through the device. The OE inputs disable
both the A and B ports by placing them in a high impedance
state.
n Separate control logic for each byte
n 16-bit version of the ’ABT245
n A and B output sink capability of 48 mA, source
capability of 24 mA
n Guaranteed latchup protection
n High impedance glitch free bus loading during entire
power up and power down cycle
n Non-destructive hot insertion capability
n Standard Microcircuit Drawing (SMD) 5962-9317501
Features
n Bidirectional non-inverting buffers
Military
54ABT16245W-QML
Package
Number
WA48A
Logic Symbol
Package Description
48-Lead Cerpack
Pin Description
Pin Names
OEn
T/Rn
A0– A15
B0– B15
Description
Output Enable Input (Active Low)
Transmit/Receive Input
Side A Inputs/Outputs
Side B Inputs/Outputs
DS100200-1
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS100200
PrintDate=1998/08/27 PrintTime=14:50:42 44961 ds100200 Rev. No. 1 cmserv Proof
www.national.com
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54ABT16245 데이터시트, 핀배열, 회로
Connection Diagram
Pin Assignment for Cerpack
Logic Diagrams
DS100200-2
Functional Description
The ’ABT16245 contains sixteen non-inverting bidirectional
buffers with TRI-STATE outputs. The device is byte con-
trolled with each byte functioning identically, but independent
of the other. The control pins can be shorted together to ob-
tain full 16-bit operation.
Truth Table
Inputs
OE1
L
T/R1
L
LH
HX
Inputs
OE2
L
T/R2
L
LH
HX
H = High Voltage Level
L = Low Voltage Level
X = Immaterial
Z = High Impedance
Outputs
Bus B0–B7 Data to Bus A0–A 7
Bus A0–A7 Data to Bus B0–B 7
HIGH-Z State on A0–A7, B0–B 7
Outputs
Bus B8–B15 Data to Bus A8–A 15
Bus A8–A15 Data to Bus B8–B 15
HIGH-Z State on A8–A15, B8–B 15
DS100200-3
DS100200-4
www.national.com
2
PrintDate=1998/08/27 PrintTime=14:50:42 44961 ds100200 Rev. No. 1 cmserv Proof
2




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