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PDF DM74AS640 Data sheet ( Hoja de datos )
| Número de pieza | DM74AS640 | |
| Descripción | 3-STATE Octal Bus Transceiver | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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October 1986
Revised March 2000
DM74AS640
3-STATE Octal Bus Transceiver
General Description
This advanced Schottky device contains 8 pairs of 3-
STATE logic elements configured as octal bus transceiver.
This circuit is designed for use in memory, microprocessor
systems and in asynchronous bidirectional data buses.
This device transmits data from the A bus to the B bus, or
vice versa, depending upon the logic level of the direction
control input (DIR). The enable input (G) can be used to
disable the devices, effecting isolation of buses A and B.
The 3-STATE circuitry also contains a protection feature
that prevents these transceivers from glitching the bus dur-
ing power-up or power-down.
Features
s Switching specifications at 50 pF
s Switching specifications guaranteed over full tempera-
ture and VCC range
s Advanced oxide-isolated, ion-implanted Schottky TTL
process
s Functionally and pin for pin compatible with Schottky,
low power Schottky, and advanced low power Schottky
TTL counterpart
s Improved AC performance over Schottky, low power
Schottky, and advanced low power Schottky counter-
parts
s 3-STATE outputs independently controlled on A and B
buses
s Low output impedance drive to drive terminated trans-
mission lines to 133Ω
s Specified to interface with CMOS at VOH = VCC − 2V
Ordering Code:
Order Number Package Number
Package Description
DM74AS640WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74AS640N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Control Inputs
G DIR
LL
L
H
H = HIGH Logic Level
L = LOW Logic Level
X = Immaterial
H
X
Logic Diagram
Operation
B Data to A Bus
A Data to B Bus
Isolation
Top View
© 2000 Fairchild Semiconductor Corporation DS006708
www.fairchildsemi.com
1 page  
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
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| Páginas | Total 5 Páginas | |
| PDF Descargar | [ Datasheet DM74AS640.PDF ] | |
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