DM74ALS646 반도체 회로 부품 판매점
Octal 3-STATE Bus Transceiver and Register
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 Fairchild Semiconductor |
October 1986
Revised February 2000
DM74ALS646
Octal 3-STATE Bus Transceiver and Register
General Description
This device incorporates an octal bus transceiver and an
octal D-type register configured to enable multiplexed
transmission of data from bus to bus or internal register to
bus.
This bus transceiver features totem-pole 3-STATE outputs
designed specifically for driving highly-capacitive or rela-
tively low-impedance loads. The high-impedance state and
increased high-logic level drive provides this device with
the capability of being connected directly to and driving the
bus lines in a bus-organized system without the need for
interface or pull-up components. They are particularly
attractive for implementing buffer registers, I/O ports, bidi-
rectional bus drivers, and working registers.
The registers in the DM74ALS646 are edge-triggered D-
type flip-flops. On the positive transition of the clock (CAB
or CBA), the input bus data is stored into the appropriate
register. The CAB input controls the transfer of data into
the A register and the CBA input controls the B register.
The SAB and SBA control pins are provided to select
whether real-time data or stored data is transferred. A LOW
input level selects real-time data, and a HIGH level selects
stored data. The select controls have a “make before
break” configuration to eliminate a glitch which would nor-
mally occur in a typical multiplexer during the transition
between store and real-time data.
The enable G and direction control pins provide four modes
of operation: real-time data transfer from bus A to B, real-
time data transfer from bus B to A, real-time bus A and/or B
data transfer to internal storage, or internally stored data
transfer to bus A or B.
When the enable G pin is LOW, the direction pin selects
which bus receives data. When the enable G pin is HIGH,
both buses become disabled yet their input function is still
enabled.
Features
s Switching specifications at 50 pF
s Switching specifications guaranteed over full tempera-
ture and VCC range
s Advanced oxide-isolated, ion-implanted Schottky TTL
process
s 3-STATE buffer outputs drive bus lines directly
s Multiplexed real-time and stored data
s Independent registers for A and B buses
Ordering Code
Order Number Package Number
Package Description
DM74ALS646WM
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74ALS646NT
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2000 Fairchild Semiconductor Corporation DS009172
www.fairchildsemi.com
Connection Diagram
Function Table
Inputs
Data I/O (Note 1)
G DIR CAB CBA SAB SBA A1 thru A8 B1 thru B8
Operation or Function
XX ↑XXX
Input
Not Specified Store A, B Unspecified
X X X ↑ X X Not Specified
Input
Store B, A Unspecified
HX ↑↑XX
Input
Input
Store A and B Data
H X H/L H/L X X
Input
Input
Isolation, Hold Storage
L LXXXL
Output
Input
Real-Time B Data to a Bus
L L X H/L X H
Output
Input
Stored B Data to a Bus
L HXX L X
Input
Output Real-Time A Data to B Bus
L H H/L X H X
Input
Output Stored A Data to B Bus
H = HIGH Logic Level
L = LOW Logic Level
X = Don’t Care (Either LOW or HIGH Logic Levels including transitions)
H/L = Either LOW or HIGH Logic Level excluding transitions
↑ = Positive going edge of pulse
Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled, i.e., data
at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.
Logic Diagram
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DM74ALS646 transceiver
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국내 전력반도체 판매점
상호 : 아이지 인터내셔날
전화번호 : 051-319-2877
[ 홈페이지 ]
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전력반도체 문의 : 010-3582-2743
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