파트넘버.co.kr FB2040A 데이터시트 PDF


FB2040A 반도체 회로 부품 판매점

8-bit Futurebus transceiver



NXP Semiconductors 로고
NXP Semiconductors
FB2040A 데이터시트, 핀배열, 회로
Philips Semiconductors
8-bit Futurebus+ transceiver
Product specification
FB2040A
FEATURES
8-bit BTL transceivers
Separate I/O on TTL A-port
Inverting
Drives heavily loaded backplanes with equivalent load
impedances down to 10.
High drive 100mA BTL open collector drivers on B-port
Allows incident wave switching in heavily loaded backplane buses
Reduced BTL voltage swing produces less noise and reduces
power consumption
Built-in precision band-gap reference provides accurate receiver
thresholds and improved noise immunity
Compatible with IEEE Futurebus+ or proprietary BTL backplanes
Controlled output ramp and multiple GND pins minimize ground
bounce
Each BTL driver has a dedicated Bus GND for a signal return
Glitch-free power up/power down operation
Low ICC current
Tight output skew
Supports live insertion
Pins for the optional JTAG boundary scan function are provided
High density packaging in plastic Quad Flat Pack
QUICK REFERENCE DATA
SYMBOL
tPLH
tPHL
tPLH
tPHL
COB
IOL
ICC
PARAMETER
Propagation delay
AIn to Bn
Propagation delay
Bn to AOn
Output capacitance (B0 – B7 only)
Output current (B0 – B7 only)
Standby
Supply current
AIn to Bn
(outputs Low or High)
Bn to AOn
(outputs Low)
Bn to AOn
(outputs High)
TYPICAL
4.4
3.1
3.4
3.2
4
100
4
4
22
12
UNIT
ns
ns
pF
mA
mA
ORDERING INFORMATION
PACKAGES
52-pin Plastic Quad Flat Pack (QFP)
COMMERCIAL RANGE
VCC = 5V±10%; Tamb = 0°C to +70°C
FB2040BB
DRAWING
NUMBER
SOT379-1
ABSOLUTE MAXIMUM RATINGS
Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free-air temperature range.
SYMBOL
PARAMETER
RATING
UNIT
VCC
VIN
IIN
VOUT
IOUT
Tamb
TSTG
Supply voltage
Input voltage
AI0 – AI7, OEB0, OEB1, OEA
B0 – B7
Input current
Voltage applied to output in High output state
Current applied to output in Low
output state
A0 – A7
B0 – B7
Operating free-air temperature range
Storage temperature
-0.5 to +7.0
-1.2 to +7.0
-1.2 to +5.5
-18 to +5.0
-0.5 to +VCC
48
200
-40 to ++85
-65 to +150
V
V
mA
V
mA
°C
°C
1995 May 25
1 853-1801 15279


FB2040A 데이터시트, 핀배열, 회로
Philips Semiconductors
8-bit Futurebus+ transceiver
PIN CONFIGURATION
Product specification
FB2040A
52 51 50 49 48 47 46 45 44 43 42 41 40
LOGIC GND 1
AI1 2
AI2 3
AO2 4
LOGIC GND 5
AO3 6
LOGIC GND 7
AI3 8
AI4 9
AO4 10
LOGIC GND 11
AO5 12
LOGIC GND 13
8-Bit Transceiver
FB2040A
52-lead PQFP
39 BUS GND
38 B1
37 BUS GND
36 B2
35 BUS GND
34 B3
33 BUS GND
32 B4
31 BUS GND
30 B5
29 BUS GND
28 B6
27 BUS GND
14 15 16 17 18 19 20 21 22 23 24 25 26
DESCRIPTION
The FB2040A is an 8-bit bidirectional BTL transceiver and is
intended to provide the electrical interface to a high performance
wired-OR bus. The FB2040A is an inverting transceiver.
The B-port drivers are Low-capacitance open collectors with
controlled ramp and are designed to sink 100mA. Precision band
gap references on the B-port insure very good noise margins by
limiting the switching threshold to a narrow region centered at 1.55V.
The B-port interfaces to “Backplane Transceiver Logic” (See the
IEEE 1194.1 BTL standard). BTL features low power consumption
by reducing voltage swing (1Vp-p, between 1V and 2V) and reduced
capacitive loading by placing an internal series diode on the drivers.
BTL also provides incident wave switching, a necessity for high
performance backplanes.
The A-port operates at TTL levels with separate I/O. The 3-state
A-port drivers are enabled when OEA goes High after an extra 6ns
delay which is built in to provide a break-before-make function.
When OEA goes Low, A-port drivers become High impedance
without any extra delay. During power on/off cycles, the A-port
drivers are held in a High impedance state when VCC is below 2.5V.
The B-port has two output enables, OEB0 and OEB1. When OEB0
is High and OEB1 is Low the output is enabled. When OEB0 is Low
SG00076
or if OEB1 is High, the B-port is inactive and is at the level of the
backplane signal.
To support live insertion, OEB0 is held Low during power on/off
cycles to insure glitch free B port drivers. Proper bias for B port
drivers during live insertion is provided by the BIAS V pin when at a
5V level while VCC is Low. If live insertion is not a requirement, the
BIAS V pin should be tied to a VCC pin.
The LOGIC GND and BUS GND pins are isolated in the package to
minimize noise coupling between the BTL and TTL sides. These
pins should be tied to a common ground external to the package.
Each BTL driver has an associated BUS GND pin that acts as a
signal return path and these BUS GND pins are internally isolated
from each other. In the event of a ground return fault, a “hard” signal
failure occurs instead of a pattern dependent error that may be very
infrequent and impossible to trouble-shoot.
The LOGIC VCC and BUS VCC pins are also isolated internally to
minimize noise and may be externally decoupled separately or
simply tied together.
JTAG boundary scan pins are provided with signals TMS, TCK, TDI
and TDO. TMS and TCK are no-connects (no bond wires) and TDI
and TDO are shorted together internally. Boundary scan
functionality is not implemented at this time.
1995 May 25
2




PDF 파일 내의 페이지 : 총 9 페이지

제조업체: NXP Semiconductors

( nxp )

FB2040A transceiver

데이터시트 다운로드
:

[ FB2040A.PDF ]

[ FB2040A 다른 제조사 검색 ]




국내 전력반도체 판매점


상호 : 아이지 인터내셔날

전화번호 : 051-319-2877

[ 홈페이지 ]

IGBT, TR 모듈, SCR, 다이오드모듈, 각종 전력 휴즈

( IYXS, Powerex, Toshiba, Fuji, Bussmann, Eaton )

전력반도체 문의 : 010-3582-2743



일반적인 전자부품 판매점


디바이스마트

IC114

엘레파츠

ICbanQ

Mouser Electronics

DigiKey Electronics

Element14


관련 데이터시트


FB2040A

8-bit Futurebus transceiver - NXP Semiconductors