M-986-2A1 판매점 - MF Transceiver

Features

• Direct A-Law or µ-Law PCM digital input

• 2.048 Mb/s clocking

• Operates with standard codecs for analog interfac-

ing

• Microprocessor read/write interface

• Binary or 2-of-6 data formats

• Dual-channel

• 5 volt power

Applications

• Test equipment

• Trunk adapters

• Paging terminals

• Traffic recorders

• PBXs

M-986-2A1

MF Transceiver

Description

The M-986-2A1 dual channel MF Transceiver con-

tains all the logic necessary to transmit and receive

(North American) CCITT Region 1 multifrequency

signals on one integrated circuit (IC).

Operating with a 20.48 MHz crystal, the M-986 is

capable of providing a direct digital interface to a m-

law or A-law encoded PCM digital input. Each channel

can be connected to an analog source using a coder-

decoder (codec) as shown in the Block Diagram

below.

The M-986 is configured and controlled through an

integral coprocessor port.

Ordering Information

Part #

M-986-2A1P

M-986-2A1PL

Description

40-pin plastic DIP

44-pin PLCC

Block Diagram

DS-M986-2A1

www.clare.com

M-986-2A1

Absolute Maximum Ratings Over Specified

Temperature Range

Supply voltage range, VCC

Input voltage range

Output voltage range

Ambient air temperature range

Storage temperature range

-0.3 V to 7 V

-0.3 V to 15 V

0˚ to 150˚C

-45˚C to 150˚C

Absolute Maximum Ratings are stress ratings. Stresses in

excess of these ratings can cause permanent damage to

the device. Functional operation of the device at these or

any other conditions beyond those indicated in the opera-

tional sections of this data sheet is not implied. Exposure of

the device to the absolute maximum ratings for an extend-

ed period may degrade the device and effect its reliability.

Function Description

The M-986-2A1 can be set up for various modes of

operation by writing two configuration bytes to the

coprocessor port. The format of the two configuration

bytes is shown in the Configuration Table on page 3

and the configuration options are described in the fol-

lowing paragraphs.

Configuration Options

External/Internal Codec Clock (ECLK): If external

codec clocking is selected, an external clocking source

provides an 8 kHz transmit framing clock and an 8 kHz

receive framing clock. It also provides a serial bit clock

with a frequency that is a multiple of 8 kHz between

216 kHz and 2.496 MHz for exchange of data via the

serial ports. When internal codec clocking is selected,

the M-986-2A1 provides an 8 kHz framing clock and a

2.048 MHz serial bit clock.

2 of 6/Binary Input/Output (IOM): When the 2-of-6

input/output is selected, the M-986-2A1 encodes the

received R1 MF tone pair into a 6-bit format, where

each bit represents one of the six possible frequencies.

A logic high level indicates the presence of a frequen-

cy. The digital input to the M-986-2A1 that selects the

transmitted R1 MF tone pair must also be coded in the

2-of-6 format.

Electrical Characteristics/Temperature Range

When binary input/output is selected, the M-986-2A1

encodes the received R1 MF tone pair into a 4 bit

binary format. The digital input to the M-986-2A1 that

selects the transmitted R1 MF tone pair must also be

coded in a 4 bit binary format.

Enable/Disable Channel (ENC): When a channel is

disabled, the receiver does not process its codec

input for R1 MF tones, and the transmitter does not

respond to transmit commands. If a transmit com-

mand is given while the channel is enabled, the “tone

off” command must be given before the channel is dis-

abled. Disabling the channel does not automatically

shut off the transmitter. When a channel is enabled,

the receiver and transmitter for that channel function

normally.

Long/Short KP Tone Detection Time (KPL): When

long KP tone detection is selected, the minimum on

time for the KP tone to be detected is 55 milliseconds.

When short KP tone detection is selected, the mini-

mum on time for the KP tone to be detected is 30 mil-

liseconds (the same as the minimum on time for the

rest of the MF tones).

Enable MF Tone Detection After Reception of KP

(KPEN): When this feature is enabled, MF tone detec-

tion is enabled after reception of the KP tone, and dis-

abled after reception of ST, ST1, ST2, or ST3 tones.

When this feature is disabled, MF tone detection is

always enabled. Select A or µ-law input/output (AMU)

for A-law encoding, this bit is set to a 1, for µ-law

encoding it is set to 0.

Parameter

Test ConditionsMin

ICC Supply current

f = 20.5 MHz, VCC = 5.5V,

TA = 0˚ to 70 ˚C

VOH High-level output voltage

IOH = MAX

IOH = 20 µ A

VOL Low-level output voltage

IOL = MAX

IOZ Off-state output current

VCC = MAX

VO = 2.4 V

VO = 0.4 V

II Input current

VI = VSS to VCC Except CLKIN

CLKIN

CI Input capacitance Data bus

All others

f = 1 MHz, all other pins 0 V

CO Output capacitance Data bus

All others

Typ

2.4

VCC -0.4

Max

0.3

Unit

0.6

-20

±20

±50

µA

2 www.clare.com

Rev. 3

M-986-2A1 반도체 회로 부품 판매점

MF Transceiver

국내 전력반도체 판매점

일반적인 전자부품 판매점

관련 데이터시트