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PDF ADF7030 Data sheet ( Hoja de datos )
| Número de pieza | ADF7030 | |
| Descripción | Radio Transceiver IC | |
| Fabricantes | Analog Devices | |
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Data Sheet
High Performance, Low Power,
169 MHz ISM Band, Radio Transceiver IC
ADF7030
FEATURES
Host microprocessor interface
RF frequency range: 169.4 MHz to 169.6 MHz
Modulation: 2 Gaussian frequency key shifting (GFSK), 4GFSK
Data rates
2GFSK: 2.4 kbps and 4.8 kbps
4GFSK: 6.4 kbps (transmitter only)
Easy to use programming interface (SPI)
Configurable output and input interrupts
Suitable for systems targeting compliance with
ETSI EN 300 220
6 mm × 6 mm, 40-lead, standard lead LFCSP
Low power consumption
1 nA sleep current
Receiver (Rx) performance
97 dB blocking at ±10 MHz offset
93 dB blocking at ±2 MHz offset
66 dB adjacent channel rejection
−122.8 dBm sensitivity at BER = 0.1%
APPLICATIONS
Wireless M-Bus Mode N (EN 13757-4)
Smart metering
Social alarms
Active tag asset tracking
GENERAL DESCRIPTION
Transmitter (Tx) performance
The ADF7030 is a low power, high performance, integrated
2 power amplifier (PA) outputs
radio transceiver supporting narrow-band operation in the
−20 dBm to +17 dBm output power range
169.4 MHz to 169.6 MHz ISM band. The ADF7030 supports
0.1 dB output power step resolution
transmit and receive operation at 2.4 kbps and 4.8 kbps using
Very low output power variation vs. temperature and supply
2GFSK modulation and transmit operation at 6.4 kbps using
61 mA Tx current at 17 dBm
Accurate digital received signal strength indication (RSSI)
Fast settling automatic frequency control (AFC) algorithm for
very short preambles
Autonomous automatic gain control (AGC) algorithm
4GFSK modulation.
The ADF7030 features an on-chip ARM® Cortex®-M0 processor
that performs radio control and calibration, as well as packet
management.
On-chip ARM Cortex-M0 processor performs the following
functions:
Radio control
Radio calibration
Packet management
FUNCTIONAL BLOCK DIAGRAM
LDOx
TCXO BUFFER
LNA
RECEIVER
PA SYNTHESIZER
PA TRANSMITTER
DIGITAL
BASEBAND
ARM
CORTEX-M0
ROM
RAM
ADF7030
INTERRUPT
CONTROLLER
SPI
SLAVE
8×
CONFIGURABLE
GPIOs
Figure 1.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADF7030
Parameter
PA2
Transmit Power
Maximum
2.8 V ≤ VDD≤ 3.6 V
2.2 V ≤ VDD≤ 3.6 V
Minimum
Step Resolution
Transmit Power Variation vs.
Temperature
Transmit Power Variation vs. VDD
Transmit Power Accuracy
ADJACENT CHANNEL POWER (ACP)
Min
2.4 kbps
Adjacent Channel
Alternate Channel
4.8 kbps
Adjacent Channel
Alternate Channel
6.4 kbps
Adjacent Channel
Alternate Channel
OCCUPIED BANDWIDTH
2.4 kbps
4.8 kbps
6.4 kbps
MAXIMUM SPURIOUS EMISSIONS
(EXCLUDING HARMONICS)
47 MHz to 74 MHz
74 MHz to 87.5 MHz
87.5 MHz to 118 MHz
118 MHz to 168.5 MHz
168.5 MHz to 170.5 MHz
170.5 MHz to 174 MHz
174 MHz to 230 MHz
230 MHz to 470 MHz
470 MHz to 862 MHz
862 MHz to 1 GHz
1 GHz to 4 GHz
Typ Max Unit Test Conditions/Comments
Data Sheet
17
13
−20
0.1
±0.1
±0.1
±0.25
−81
−81
−59
−77
−68
−79
6.3
7.8
8.1
−84
<−87
−87
−79
−69
−80
−84
−82
−84
<−87
<−87
The maximum output power level achievable on PA2
depends on the programmable PA LDO setting
dBm
dBm
dBm
dB
dB From −40°C to +85°C, transmit power = 17 dBm
dB From VDD = 3.0 V to VDD = 3.6 V, transmit power = 17 dBm
dB Transmit power = 17 dBm
Measured according to ETSI EN 300 220-1 V2.4.1;
12.5 kHz channel spacing; spectrum analyzer settings:
measurement bandwidth (BW) = 8.5 kHz, resolution band-
width (RBW) = 100 Hz, video bandwidth (VBW) = 300 Hz
2GFSK, frequency deviation = 2.4 kHz, PA1, output
power = 13 dBm
dBc
dBc
2GFSK, frequency deviation = 2.4 kHz, PA2, output
power = 17 dBm
dBc
dBc
4GFSK, frequency deviation = 3.2 kHz, PA1, output
power = 13 dBm
dBc
dBc
Occupied bandwidth is the bandwidth containing 99% of
the total integrated power; spectrum analyzer settings:
measurement BW = 8.5 kHz, RBW = 100 Hz, VBW = 300 Hz
kHz 2GFSK, frequency deviation = 2.4 kHz, PA1, output
power = 13 dBm
kHz 2GFSK, frequency deviation = 2.4 kHz, PA2, output
power = 17 dBm
kHz 4GFSK, frequency deviation = 3.2 kHz, PA1, output
power = 13 dBm
Measured according to ETSI EN 300 220-1 V2.4.1 on the
ADF7030 evaluation board; transmitting continuous
PN9 data on PA1 at 13 dBm
dBc
dBc
dBc
dBc
dBc Excluding frequency range fCHANNEL ± 31.25 kHz
dBc
dBc
dBc
dBc
dBc
dBc
Rev. 0 | Page 4 of 24
5 Page 
ADF7030
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Data Sheet
RST 1
VBAT1 2
CREG1 3
VBAT2 4
CREG2 5
LNAIN1 6
LNAIN2 7
DNC 8
CREG3 9
DNC 10
ADF7030
TOP VIEW
(Not to Scale)
30 DNC
29 GPIO6
28 CS
27 SCLK
26 MISO
25 MOSI
24 VBAT5
23 VBAT4
22 GPIO5
21 GPIO4
NOTES
1. DNC = DO NOT CONNECT.
2. CONNECT THE EXPOSED PAD TO GROUND.
Figure 4. Pin Configuration
Table 8. Pin Function Descriptions
Pin No. Mnemonic Description
1 RST
External Reset, Active Low.
2
VBAT1
Power Supply Pin 1 to the Internal Regulators.
3
CREG1
Regulator Output 1. Place a 220 nF capacitor between this pin and ground for regulator stability and noise
rejection. Also, place a 1.2 nF capacitor between this pin and the CLF pin.
4
VBAT2
Power Supply Pin 2 to the Internal Regulators.
5
CREG2
Regulator Output 2. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection.
6
LNAIN1
LNA Input 1.
7
LNAIN2
LNA Input 2.
8 DNC
Do Not Connect. Do not connect to this pin.
9
CREG3
Regulator Output 3. Connect to the PA choke inductor to provide bias to the PA. Place a 220 nF capacitor between
this pin and ground for regulator stability and noise rejection.
10 DNC
Do Not Connect. Do not connect to this pin.
11 DNC
Do Not Connect. Do not connect to this pin.
12
PAOUT1
Single-Ended PA1 Output.
13
PAOUT2
Single-Ended PA2 Output.
14 VBAT3 Power Supply Pin 3 to the Internal Regulators.
15 CREG4 Regulator Output 4. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection.
16 GPIO0 Digital General-Purpose Input/Output (GPIO) Pin 0.
17 GPIO1 Digital GPIO Pin 1.
18 GPIO2 Digital GPIO Pin 2.
19 GPIO3 Digital GPIO Pin 3.
20 DNC
Do Not Connect. Do not connect to this pin.
21 GPIO4 Digital GPIO Pin 4.
22 GPIO5 Digital GPIO Pin 5.
23 VBAT4 Power Supply Pin 4 to the Internal Regulators.
24 VBAT5 Power Supply Pin 5 to the Internal Regulators.
25 MOSI
Serial Port Master Out/Slave In.
26 MISO
Serial Port Master In/Slave Out.
27 SCLK
Serial Port Clock.
28 CS
Chip Select (Active Low). A pull-up resistor of 100 kΩ to VDD is recommended to prevent the host processor from
inadvertently waking the ADF7030 from sleep.
Rev. 0 | Page 10 of 24
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet ADF7030.PDF ] | |
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