|
|
PDF 74ALVCH32973 Data sheet ( Hoja de datos )
| Número de pieza | 74ALVCH32973 | |
| Descripción | 16-bit bus transceiver and transparant D-type latch | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de 74ALVCH32973 (archivo pdf) en la parte inferior de esta página. Total 17 Páginas | ||
|
No Preview Available !
74ALVCH32973
16-bit bus transceiver and transparant D-type latch with 8
independent buffers
Rev. 3 — 17 January 2013
Product data sheet
1. General description
The 74ALVCH32973 is a 16-bit bus transceiver and transparent D-type latch with 8
independent buffers with bus hold inputs and 3-state outputs. It features direction (1DIR,
2DIR), latch enable (1LOE, 2LOE), transceiver output enable (1TOE, 2TOE) and latch
enable (1LE, 2LE) control inputs; four 8-bit transceiver ports (1An, 2An & 1Bn, 2Bn); two
8-bit D-type latch output ports (1Qn, 2Qn) and an 8-bit buffer with data inputs Dn and
outputs Yn. The configuration of the control pins allows the device to be used as one 8-bit
buffer, two 8-bit transceivers, and two 8-bit latches or one 8-bit buffer, one 16-bit
transceiver and one 16-bit latch.
The 8-bit buffer functions independently of the control inputs. The direction of data
transmission between A and B is controlled by nDIR and when nTOE is set HIGH the A
and B ports will assume a HIGH-impedance OFF-state, they will be effectively isolated.
When nLE is HIGH, data at the A inputs enter the latches. In this condition the latches are
transparent, a Q output will change each time its corresponding A-input changes. When
nLE is LOW the latches store the information that was present at the inputs a set-up time
preceding the HIGH-to-LOW transition of nLE. A HIGH on nLOE causes the Q outputs to
assume a high-impedance OFF-state. Operation of the nLOE input does not affect the
state of the latches.
2. Features and benefits
Wide supply voltage range from 1.2 V to 3.6 V
Complies with JEDEC standard JESD8-B
CMOS low power consumption
Direct interface with TTL levels
All data inputs have bus hold
Output drive capability 50 transmission lines at 85 C
Current drive 24 mA at VCC = 3.0 V
1 page  
NXP Semiconductors
74ALVCH32973
16-bit bus transceiver and transparant D-type latch; 8 buffers
7. Limiting values
Table 6. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min Max Unit
VCC
IIK
VI
IOK
VO
IO
ICC
IGND
Tstg
Ptot
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
VI < 0 V
control inputs
data inputs
VO > VCC or VO < 0 V
VO = 0 V to VCC
Tamb = 40 C to +85 C
0.5
50
[1] 0.5
[1] 0.5
-
[1] 0.5
-
-
100
65
[2] -
+4.6
-
+4.6
VCC + 0.5
50
VCC + 0.5
50
100
-
+150
1 000
V
mA
V
V
mA
V
mA
mA
mA
C
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] Above 70 C the value of Ptot derates linearly with 1.8 mW/K.
8. Recommended operating conditions
Table 7.
Symbol
VCC
VI
VO
Tamb
t/V
Recommended operating conditions
Parameter
Conditions
supply voltage
maximum speed performance
CL = 30 pF
CL = 50 pF
low voltage applications
input voltage
output voltage
ambient temperature
in free air
input transition rise and fall rate VCC = 2.3 V to 3.0 V
VCC = 3.0 V to 3.6 V
Min Typ Max Unit
2.3 -
3.0 -
1.2 -
0-
0-
40 -
0-
0-
2.7 V
3.6 V
3.6 V
VCC
V
VCC
V
+85 C
20 ns/V
10 ns/V
74ALVCH32973
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 17 January 2013
© NXP B.V. 2013. All rights reserved.
5 of 17
5 Page 
NXP Semiconductors
74ALVCH32973
16-bit bus transceiver and transparant D-type latch; 8 buffers
'Q LQSXW
9,
*1'
92+
<Q RXWSXW
92/
90
W3+/
90
90
W3/+
90
DDD
Fig 7.
Measurement points are given in Table 10.
VOL and VOH are typical output levels that occur with the output load.
Propagation delay, input (Dn) to data output (Yn)
9,
Q72( Q/2( LQSXW
*1'
RXWSXW
/2:WR2))
2))WR/2:
9&&
92/
RXWSXW
+,*+WR2))
2))WR+,*+
92+
*1'
90
W3/=
W3=/
W3+=
9;
9<
90
W3=+
90
RXWSXWV
HQDEOHG
RXWSXWV
GLVDEOHG
RXWSXWV
HQDEOHG
DDD
Fig 8.
Measurement points are given in Table 10.
VOL and VOH are typical output levels that occur with the output load.
3-state enable and disable times
9,
Q$Q LQSXW
*1'
9,
Q/( LQSXW
*1'
90
WVX
WK
90
WK
WVX
DDD
Fig 9.
Measurement points are given in Table 10.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Data setup and hold times for input (nAn) to input (nLE)
74ALVCH32973
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 17 January 2013
© NXP B.V. 2013. All rights reserved.
11 of 17
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet 74ALVCH32973.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| 74ALVCH32973 | 16-bit bus transceiver and transparant D-type latch | NXP Semiconductors |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |