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PDF 74LCXH16245 Data sheet ( Hoja de datos )
| Número de pieza | 74LCXH16245 | |
| Descripción | LOW VOLTAGE CMOS 16-BIT BUS TRANSCEIVER | |
| Fabricantes | STMicroelectronics | |
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74LCXH16245
LOW VOLTAGE CMOS 16-BIT BUS TRANSCEIVER
WITH 5V TOLERANT INPUTS AND OUTPUT (3-STATE)
s 5V TOLERANT INPUTS AND OUTPUTS
s HIGH SPEED:
tPD = 4.5 ns (MAX.) at VCC = 3V
s POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24mA (MIN) at VCC = 3V
s PCI BUS LEVELS GUARANTEED AT 24 mA
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s OPERATING VOLTAGE RANGE:
VCC(OPR) = 2.0V to 3.6V (1.5V Data
Retention)
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES H16245
s BUS HOLD PROVIDED ON BOTH SIDES
s LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
s ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
DESCRIPTION
The 74LCXH16245 is a low voltage CMOS 16 BIT
BUS TRANSCEIVER (3-STATE) fabricated with
sub-micron silicon gate and double-layer metal
wiring C2MOS technology. It is ideal for low power
and high speed 3.3V applications; it can be
interfaced to 5V signal environment for both inputs
and outputs.
This IC is intended for two-way asynchronous
communication between data buses; the direction
of data transmission is determined by DIR input.
The two enable inputs nG can be used to disable
the device so that the buses are effectively isolat-
ed.
Bus hold on data inputs is provided in order to
eliminate the need for external pull-up or
pull-down resistor.
It has same speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power con-
sumption.
All inputs and outputs are equipped with protec-
tion circuits against static discharge, giving them
2KV ESD immunity and transient excess voltage.
All floating bus terminals during High Z State must
be held HIGH or LOW.
July 2003
TSSOP
ORDER CODES
PACKAGE
TSSOP
TUBE
PIN CONNECTION
T&R
74LCXH16245TTR
1/10
1 page  
74LCXH16245
AC ELECTRICAL CHARACTERISTICS
Test Condition
Value
Symbol
Parameter
VCC
CL RL ts = tr -40 to 85 °C
-55 to 125 °C Unit
(V) (pF) (Ω) (ns) Min. Max. Min. Max.
tPLH tPHL Propagation Delay
Time
2.7
3.0 to 3.6
50 500 2.5
1.5
1.5
5.2
4.5
1.5
1.5
6.0
5.3
ns
tPZL tPZH Output Enable Time
2.7
1.5 7.2 1.5 8.3
50 500 2.5
ns
3.0 to 3.6
1.5 6.5 1.5 7.3
tPLZ tPHZ Output Disable Time
2.7
1.5 6.9 1.5 7.5
50 500 2.5
ns
3.0 to 3.6
1.5 6.4 1.5 7.2
tOSLH
tOSHL
Output To Output
Skew Time (note1,
2)
3.0 to 3.6
50 500 2.5
1.0
1.0 ns
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (tOSLH = | tPLHm - tPLHn|, tOSHL = | tPHLm - tPHLn|)
2) Parameter guaranteed by design
CAPACITIVE CHARACTERISTICS
Test Condition
Value
Symbol
Parameter
VCC
(V)
TA = 25 °C
Min. Typ. Max.
Unit
CIN Input Capacitance
3.3
4 pF
COUT Output Capacitance
3.3
10 pF
CPD Power Dissipation Capacitance
(note 1)
3.3
fIN = 10MHz
VIN = 0 or VCC
50
pF
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/16 (per
circuit)
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5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet 74LCXH16245.PDF ] | |
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