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PDF 74LCXHR162245 Data sheet ( Hoja de datos )
| Número de pieza | 74LCXHR162245 | |
| Descripción | LOW VOLTAGE CMOS 16-BIT BUS TRANSCEIVER | |
| Fabricantes | STMicroelectronics | |
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74LCXHR162245
LOW VOLTAGE CMOS 16-BIT BUS TRANSCEIVER
WITH 5V TOLERANT INPUTS AND OUTPUT (3-STATE)
s 5V TOLERANT INPUTS AND OUTPUTS
s HIGH SPEED:
tPD = 4.7 ns (MAX.) at VCC = 3V
s POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 12mA (MIN) at VCC = 3V
s PCI BUS LEVELS GUARANTEED AT 12 mA
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s OPERATING VOLTAGE RANGE:
VCC(OPR) = 2.0V to 3.6V (1.5V Data
Retention)
s BUS HOLD PROVIDED ON BOTH SIDES
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 16245
s LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
s ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
DESCRIPTION
The 74LCXHR162245 is a low voltage CMOS 16
BIT BUS TRANSCEIVER (3-STATE) fabricated
with sub-micron silicon gate and double-layer
metal wiring C2MOS technology. It is ideal for low
power and high speed 3.3V applications; it can be
interfaced to 5V signal environment for both inputs
and outputs.
This IC is intended for two-way asynchronous
communication between data buses; the direction
of data transmission is determined by DIR input.
The two enable inputs nG can be used to disable
the device so that the buses are effectively isolat-
ed.
Bus hold on data inputs is provided in order to
eliminate the need for external pull-up or
pull-down resistor.
All outputs, which are designed to sink up to
12mA, include 26Ω resistors to reduce overshoot
and undershoot.
All inputs and outputs are equipped with protec-
tion circuits against static discharge, giving them
2KV ESD immunity and transient excess voltage.
TSSOP
ORDER CODES
PACKAGE
TUBE
TSSOP
PIN CONNECTION
T&R
74LCXHR162245TTR
July 2003
1/10
1 page  
74LCXHR162245
AC ELECTRICAL CHARACTERISTICS
Test Condition
Value
Symbol
Parameter
VCC
CL RL ts = tr -40 to 85 °C
-55 to 125 °C Unit
(V) (pF) (Ω) (ns) Min. Max. Min. Max.
tPLH tPHL Propagation Delay
Time
2.7
3.0 to 3.6
50 500 2.5
1.5
1.5
4.9
4.5
1.5
1.5
5.2
4.7
ns
tPZL tPZH Output Enable Time
2.7
1.5 6.0 1.5 6.2
50 500 2.5
ns
3.0 to 3.6
1.5 5.4 1.5 5.6
tPLZ tPHZ Output Disable Time
2.7
1.5 6.0 1.5 6.2
50 500 2.5
ns
3.0 to 3.6
1.5 5.5 1.5 5.7
tOSLH
tOSHL
Output To Output
Skew Time (note1,
2)
3.0 to 3.6
50 500 2.5
1.0
1.0 ns
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (tOSLH = | tPLHm - tPLHn|, tOSHL = | tPHLm - tPHLn|)
2) Parameter guaranteed by design
CAPACITIVE CHARACTERISTICS
Test Condition
Value
Symbol
Parameter
VCC
(V)
TA = 25 °C
Min. Typ. Max.
Unit
CIN Input Capacitance
3.3 VIN = 0 to VCC
7 pF
COUT Output Capacitance
3.3 VIN = 0 to VCC
8 pF
CPD Power Dissipation Capacitance
(note 1)
3.3
fIN = 10MHz
VIN = 0 or VCC
80
pF
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/16 (per
circuit)
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| PDF Descargar | [ Datasheet 74LCXHR162245.PDF ] | |
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