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PDF NOIV1SN016KA Data sheet ( Hoja de datos )
| Número de pieza | NOIV1SN016KA | |
| Descripción | VITA 16/12 MegaPixels Single Foot Print CMOS Image Sensor | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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NOIV1SN016KA,
NOIV1SN012KA
VITA 16/12 MegaPixels
Single Foot Print CMOS
Image Sensor
www.onsemi.com
Features
• Active Pixel Array:
♦ 16K = 4096 × 4096 Active Pixels
♦ 12K = 4096 × 3072 Active Pixels
• Optical Format:
♦ 16K = APS−C Optical Format
♦ 12K = 4/3 inch Optical Format
• 4.5 mm × 4.5 mm Square Pixels
• 32/16 Low-Voltage Differential Signaling (LVDS) High-speed
Serial Outputs
• VITA 16K Frame Rate at Full Resolution, 32 LVDS Outputs
♦ 80 Frames per Second normal ROT
♦ 125 Frames per Second Zero ROT
• VITA 12K Frame Rate at Full Resolution, 32 LVDS Outputs
♦ 110 Frames per Second normal ROT
♦ 160 Frames per Second Zero ROT
• Monochrome (SN), Color (SE)
• On-chip 10-bit Analog-to-Digital Converter (ADC)
Figure 1. VITA 16K/12K Photograph
• 8-bit or 10-bit Output Mode
• 32 Random Programmable Region of Interest (ROI)
readout
Applications
• Pipelined and Triggered Global Shutter, Rolling Shutter
• Machine Vision
• Serial Peripheral Interface (SPI)
• Motion Monitoring
• Operational Temperature Range: -40°C to +85°C
• Intelligent Traffic Systems (ITS)
• Single 355−pin mPGA package across resolutions
• Pick and Place Machines
• Power Dissipation: 4.1 W @ 2 Gpix/s
• Inspection
• These Devices are Pb−Free and are RoHS Compliant
• Metrology
Description
The high-resolution VITA CMOS image sensor family features global and rolling shutter mode. The on-chip programmable
state machine controls the sensor array and enables high flexibility with changes in operation modes and 32 frame-to-frame
configurable Regions-of-Interest (ROI). The 5T pixel on a 4.5 mm pitch enables pipelining of integration and read-out in both
triggered and un-triggered global shutter mode.
A second pipeline stage provides a maximum frame rate increase by allowing the sensor to run in Zero-ROT mode. The roller
shutter mode supports correlated double sampling, reducing temporal noise by approximately 3 dB. The sensor has on-chip
programmable gain amplifiers and 10-bit A/D converters. The image’s black level has an automatic calibration with adjustable
user programmable offset. The image data interface consists of 32 or 16 LVDS channels with additional clock and
synchronization channels in parallel, each running at 680 Mbps.
The high-resolution VITA family is packaged in a ceramic 355-pin PGA package and is available in a monochrome and color
version.
Contact your local ON Semiconductor office for more information.
© Semiconductor Components Industries, LLC, 2015
May, 2015 − Rev. 0
1
Publication Order Number:
NOIV1SN016KA/D
1 page  
NOIV1SN016KA, NOIV1SN012KA
Table 5. POWER SUPPLY RATINGS
Limits in bold apply for for TJ = TMIN to TMAX, all other limits TJ = +30°C [5], [6], [7], [8]
Parameter
Description
Min Typ Max Units
LVDS Electrical/Interface
fin Input clock rate for 10-bit mode
340 MHz
fin Input clock rate for 8-bit mode
272 MHz
tidc Input clock duty cycle
45 50 55
%
tj Input clock jitter
20 ps
fspi SPI clock rate
10 MHz
ratspi
10-bit: ratio: Fin/fspi
30
8-bit: ratio: Fin/fspi
24
5. All parameters are characterized for DC conditions after thermal equilibrium is established.
6. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is recommended
that normal precautions be taken to avoid application of any voltages higher than the maximum rated voltages to this high−impedance circuit.
7. Minimum and maximum limits are guaranteed through test and design.
8. Vref_colmux supply should be able to source and sink current
Disclaimer: Image sensor products and specifications are subject to change without notice. Products are warranted to meet
the production data sheet and acceptance criteria specifications only.
Table 6. FRAME RATE
Parameter
fps_roi1
fps_roi2
fps_roi3
fps_roi4
fps_roi5
fps_roi6
fps_roi7
fps_roi8
fps_roi9
Xres × Yres = 4096 × 4096
Xres × Yres = 4096 × 3072
Xres × Yres = 3072 × 3072
Xres × Yres = 2048 × 2048
Xres × Yres = 1920 × 1080
Xres × Yres = 1024 × 1024
Xres × Yres = 640 × 480
Xres × Yres = 512 × 512
Xres × Yres = 256 × 256
Description
32 LVDS Channels
Zero ROT
Disabled Enabled
80 125
110 160
130 215
245 470
470 880
640 920
1475
1860
1450
1760
2925
3210
Units
fps
fps
fps
fps
fps
fps
fps
fps
fps
www.onsemi.com
5
5 Page 
NOIV1SN016KA, NOIV1SN012KA
External Trigger
Integration Time
Handling
Reset
N
Exposure Time N
FOT
Reset
N+1
Exposure T im e N+1
FOT
Readout
Handling
FOT
Readout N−1
FOT
Readout N
FOT
ROÉÉT ÉÉLinÉÉeReaÉÉdout ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
Figure 8. Pipelined Shutter Operated in Slave Mode
Triggered Global Shutter
In this mode, manual intervention is required to control
both the integration time and the start of readout. After the
integration time, indicated by a user controlled pin, the
image core is read out. After this sequence, the sensor goes
to an idle mode until a new user action is detected.
The three main differences from the pipelined shutter
master mode are:
• Upon user action, a single image is read.
• Normally, integration and readout are done
sequentially. However, the user can control the sensor
in such a way that two consecutive batches are
overlapping, that is, having concurrent integration and
readout.
• Integration and readout is user-controlled through an
external pin.
The triggered global mode can also be controlled in a
master or in a slave mode.
Master Mode
As shown in Figure 9, in the master mode a rising edge on
the synchronization pin is used to trigger the start of
integration and readout. The integration time is defined by
a register setting. The sensor autonomously integrates
during this predefined time, after which the FOT starts and
the image array is read out sequentially. A falling edge on the
synchronization pin does not have any impact on the readout
or integration and subsequent frames are started again for
each rising edge.
Slave Mode
Integration time control is identical to the pipelined
shutter slave mode, in which both integration time and
readout requests are controlled by an external trigger. An
external synchronization pin controls the start of integration.
The moment it is deasserted, the FOT starts. At this time, the
analog value on the pixel diode is transferred to the pixel
memory element and the image readout can start. A request
for a new frame is started when the synchronization pin is
asserted again.
External Trigger
No effect on falling edge
Integration Tim e
Handling
Readout
Handling
Reset
N
Exposure Tim e N
Register Controlled
FOT
Reset
N+1
Exposure Tim e N +1
FOT
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉFOT
Readout N -1
FOT
Readout N
FOT
ROT
Line Readout
Figure 9. Triggered Shutter Operated in Master Mode
www.onsemi.com
11
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