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PDF NOIL1SN3000A Data sheet ( Hoja de datos )
| Número de pieza | NOIL1SN3000A | |
| Descripción | High Speed CMOS Sensor | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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NOIL1SN3000A
LUPA3000: 3 MegaPixel
High Speed CMOS Sensor
Features
• 1696 x 1710 Active Pixels
• 8 mm x 8 mm Square Pixels
• 1.2 inch Optical Format
• Monochrome or Color Digital Output
• 485 Frames per Second (fps) Frame Rate
• 64 On-Chip 8-Bit ADCs
• 32 Low−Voltage Digital Signaling (LVDS) Serial Outputs
• Random Programmable Region of Interest (ROI) Readout
• Pipelined and Triggered Global Shutter
• Serial Peripheral Interface (SPI)
• Dynamic Range Extended by Double Slope
• Limited Supplies: Nominal 2.5 V and 3.3 V
• 0°C to 60°C Operational Temperature Range
• 369-Pin mPGA Package
• 1.1 W Power Dissipation
• These Devices are Pb−Free and are RoHS Compliant
http://onsemi.com
Applications
• High Speed Machine Vision
• Holographic Data Storage
• Motion Analysis
• Intelligent Traffic System
• Medical Imaging
• Industrial Imaging
Figure 1. LUPA3000 Package Photo
Description
The LUPA3000 is a high-speed CMOS image sensor with an image resolution of 1696 by 1710 pixels. The pixels are 8 mm
x 8 mm in size and consist of high sensitivity 6T pipelined global shutter capability where integration during readout is
possible. The LUPA3000 delivers 8-bit color or monochrome digital images with a 3 Megapixels resolution at 485 fps that
makes this product ideal for high-speed vision machine, intelligent traffic system, and holographic data storage. The
LUPA3000 captures complex high-speed events for traditional machine vision applications and various high-speed imaging
applications.
The LUPA3000 production package is housed in a 369-pin ceramic mPGA package and is available in a monochrome
version or Bayer (RGB) patterned color filter array with micro lens. Contact your local ON Semiconductor representative for
more information.
ORDERING INFORMATION
Marketing Part Number
Mono / Color
NOIL1SN3000A-GDC
NOIL1SE3000A-GDC
Mono micro lens with glass
Color micro lens with glass
NOTE: Refer to Ordering Code Definition on page 54 for more information.
Package
369−pin mPGA
© Semiconductor Components Industries, LLC, 2012
June, 2012 − Rev. 9
1
Publication Order Number:
NOIL1SN3000A/D
1 page  
NOIL1SN3000A
Table 7. AC ELECTRICAL CHARACTERISTICS (Note 1)
The following specifications apply for VDD = 2.5 V
Symbol
Parameter
Condition
FCLK
Input clock frequency
fps = 485
fps Frame rate
Maximum clock speed
1. All parameters are characterized for DC conditions after thermal equilibrium is established.
Typ Max Units
206 MHz
485 fps
Combining Power Supplies
Every module in the image sensor has its own power
supply and ground. The grounds can be combined
externally, but not all power supply inputs may be combined.
Some power supplies must be isolated to reduce electrical
crosstalk and improve shielding, dynamic range, and output
swing. Internal to the image sensor, the ground lines of each
module are kept separate to improve shielding and electrical
crosstalk between them.
The LUPA3000 contains circuitry to protect the inputs
against damage due to high static voltages or electric fields.
However, take normal precautions to avoid voltages higher
than the maximum rated voltages in this high-impedance
circuit. All power supply pins should be decoupled to
ground with a 100 nF capacitor. The Vpix and Vres_ds
power are the most sensitive to power supply noise.
The recommended combinations of supplies are:
• Analog group of +2.5 V supply: VRES_DS, VADC, Vpix,
VANA
• Digital Group of +2.5 V supply: VDD, VD_HS, VLVDS
• The VMEM_L and VPRECHARGE supplies should have
sinking and sourcing capability
Biasing
The sensor requires three biasing resistors. Refer to
Table 8 for more information.
For low frame rates (< 2000 fps), the
PRECHARGE_BIAS_1 pins are connected directly with
the VPRECHARGE pins. The DC level on the
PRECHARGE_BIAS_1 pins acts as a power supply and
must be decoupled.
For higher frame rates, the duty cycle on VPRECHARGE
is too high and the voltage drops. This causes the black level
to shift compared to the low frame rate case. In higher frame
rates, the voltage on PRECHARGE_BIAS_1 is buffered on
the PCB and the buffered voltage is taken for
VPRECHARGE. A second possibility is to make the biasing
resistor larger until the correct DC level is reached.
PRECHARGE_BIAS_2 must be left floating, because it
is intended for testing purposes.
Table 8. BIASING RESISTORS
Signal
Comment
Current_Ref_1
Current_Ref_2
Precharge_Bias_1
Connect with 20 kW (1% prec.) to VAA. Decouple to GNDAA
Connect with 50 kW (1% prec.) to GNDADC. No decoupling
Connect with 90 kW (1% prec.) to VPIX. Decouple to Vpix with
100 nF.
Precharge_Bias_2 Leave floating
Related Module
Column amplifiers
ADCs
Pixel array
DC level
769 mV at 86 mA
25 mA to gnd
0.45 V at 23 mA
http://onsemi.com
5
5 Page 
NOIL1SN3000A
The ADCs are designed using fully differential circuits to
improve performance and noise immunity. In addition, a
redundant signed digit (RSD) 1.5 bit per stage architecture
with digital error correction is used to improve differential
nonlinearity (DNL) and ensure that no codes are missing.
Interstage ADC gain errors are addressed using
commutation techniques for capacitor matching.
Auto-zeroing and other calibration methods are
implemented to remove offsets.
References and Programmable Trimming
Bits 6:4 of SPI register 64 (decimal) allow adjustment of
the Vrefp-Vrefm differential ADC reference level. Eight
settings are provided to enable trimming of the dynamic
range. Reduced dynamic range is used to optimize signals in
low light intensity, where reduced pixel levels require
further gain. Table 10 provides the permitted trim settings.
Table 10. PROGRAMMABLE ADC REFERENCE
LEVEL
Register Address 64
(dec)
Bit 6 Bit 5 Bit 4
Vrefp-Vrefm
Gain Level
(typ)
Comments
000
0.5x Maximum effective
gain +6.0 dB (2x)
001
0.67x
010
0.71x
011
0.77x
100
0.83x
101
0.91x
Available setting to
ensure 0 code
110
0.95x
Available setting to
ensure 0 code
111
1.0 x
POR (startup)
default level
The black voltage level from the pixel array is more
positive than the user set Vdark or “black” reference level.
This results in a nonzero differential voltage in the PGAs and
other AFE stages. This condition prevents obtaining a
desired 0 code out of the ADCs. The 0.95x and 0.91x trim
settings are specifically supplied to allow minor adjustment
to the ADC differential reference (Vrefp-Vrefm) to ensure a
zero level code in these conditions.
The additional trim settings are provided as dynamic
range adjustments in low light intensities to act as effective
global gain settings. The absolute level of gain (from the
typical values) is not guaranteed. However, the gain
increases are monotonic. Using this method, you can obtain
a maximum gain of approximately 2x (+6.0 dB). As a result,
the combined gain of both PGAs and the ADC reference
trimming available is 8x maximum.
Some reference voltages are overdriven after the on-chip
control logic is powered down (refer section On−Chip
BandGap Reference and Current Biasing on page 17).
Overdriving, a feature intended for testing and debugging,
is not recommended for normal operation. The reference
voltages that are overdriven are:
• Vrefp - Vrefm (can be overdriven as a pair)
• Vcm
• Vdark
• Internal bandgap voltage
Table 11 summarizes the ADC and AFE (signal
processing) parameters.
Each pair of odd and even kernel AFE + ADC channels are
individually powered down with its associated LVDS
serialization channel. This is controlled through bits in SPI
registers 66–70 (decimal). Logic 1 is the power down state.
The POR defaults are logic 0 for all channels powered on.
Table 11. AFE AND ADC PARAMETERS
Parameter
Parameter Value (typical)
Input range
1.5 V to 0.3 V
(single to differential converter; S2D) (SE to unipolar differential)
Vblack
1.2 V to 1.5 V (typical)
Analog PGA gain and settings
Input range (ADC)
ADC type
ADC resolution
Sampling rate per ADC
ENOB
Differential nonlinearity (DNL)
Integral nonlinearity (INL)
Power supply
1x to 4x (6 gain settings)
0.75 V to 1.75 V
Pipelined (four ADC clock latency)
8 bits
26.5 MSPS
7.5 bits
±0.5 LSB
±1.0 LSB
2.5 V ±0.25 V
Comment
S2D performs inversion. Referenced from Vblack
Dark or black level reference from SPI programmable
DAC. 0.01 mF to gnd
3-bit SPI programmable. 1x, 1.5x, 2x, 2.25x, 3x, 4x
1 V maximum Vrefp-Vrefm (2 Vp-p maximum)
With digital error correction (no missing codes)
Maximum 30 MSPS
Effective number of bits
No missing codes
http://onsemi.com
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