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PDF TMP102 Data sheet ( Hoja de datos )
| Número de pieza | TMP102 | |
| Descripción | Low Power Digital Temperature Sensor | |
| Fabricantes | Burr-Brown Corporation | |
| Logotipo |  |
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BurrĆBrown Products
from Texas Instruments
TMP102
SBOS397 – AUGUST 2007
Low Power Digital Temperature Sensor
With SMBus™/Two-Wire Serial Interface in SOT563
FEATURES
• TINY SOT563 PACKAGE
• ACCURACY: 0.5°C (–25°C to +85°C)
• LOW QUIESCENT CURRENT:
10μA Active (max)
1μA Shutdown (max)
• SUPPLY RANGE: 1.4V to 3.6V
• RESOLUTION: 12 Bits
• DIGITAL OUTPUT: Two-Wire Serial Interface
APPLICATIONS
• PORTABLE AND BATTERY-POWERED
APPLICATIONS
• POWER-SUPPLY TEMPERATURE
MONITORING
• COMPUTER PERIPHERAL THERMAL
PROTECTION
• NOTEBOOK COMPUTERS
• BATTERY MANAGEMENT
• OFFICE MACHINES
• THERMOSTAT CONTROLS
• ELECTROMECHANICAL DEVICE
TEMPERATURES
• GENERAL TEMPERATURE MEASUREMENTS:
Industrial Controls
Test Equipment
Medical Instrumentations
DESCRIPTION
The TMP102 is a two-wire, serial output temperature
sensor available in a tiny SOT563 package.
Requiring no external components, the TMP102 is
capable of reading temperatures to a resolution of
0.0625°C.
The TMP102 features SMBus and two-wire interface
compatibility, and allows up to four devices on one
bus. It also features an SMB alert function.
The TMP102 is ideal for extended temperature
measurement in a variety of communication,
computer, consumer, environmental, industrial, and
instrumentation applications. The device is specified
for operation over a temperature range of –40°C to
+125°C.
Temperature
SCL 1
Diode
Temp.
Sensor
Control
Logic
6 SDA
GND
2 DS
A/D
Converter
Serial
Interface
5
V+
ALERT
3
OSC
Config.
and Temp.
Register
4
ADD0
TMP102
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SMBus is a trademark of Intel, Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
1 page  
TMP102
www.ti.com
SBOS397 – AUGUST 2007
APPLICATION INFORMATION
The TMP102 is a digital temperature sensor that is
optimal for thermal-management and thermal-
protection applications. The TMP102 is two-wire- and
SMBus interface-compatible, and is specified over a
temperature range of –40°C to +125°C.
Pull-up resistors are required on SCL, SDA, and
ALERT. A 0.01μF bypass capacitor is recommended,
as shown in Figure 7.
V+
0.01mF
5
POINTER REGISTER
Figure 8 shows the internal register structure of the
TMP102. The 8-bit Pointer Register of the device is
used to address a given data register. The Pointer
Register uses the two LSBs (see Table 11) to
identify which of the data registers should respond to
a read or write command. Table 1 identifies the bits
of the Pointer Register byte. During a write
command, P2 through P7 must always be '0'.
Table 2 describes the pointer address of the
registers available in the TMP102. Power-up reset
value of P1/P0 is '00'. By default, the TMP102 reads
the temperature on power-up.
To
Two-Wire
Controller
SCL
SDA
14
6 TMP102 3
ADD0
ALERT
(Output)
Pointer
Register
2
NOTE: SCL, SDA, and ALERT
pins require pull-up resistors.
GND
Figure 7. Typical Connections
The temperature sensor in the TMP102 is the chip
itself. Thermal paths run through the package leads,
as well as the plastic package. The lower thermal
resistance of metal causes the leads to provide the
primary thermal path.
To maintain accuracy in applications requiring air or
surface temperature measurement, care should be
taken to isolate the package and leads from ambient
air temperature. A thermally-conductive adhesive is
helpful in achieving accurate surface temperature
measurement.
Temperature
Register
Configuration
Register
TLOW
Register
THIGH
Register
I/O
Control
Interface
SCL
SDA
Figure 8. Internal Register Structure
Table 1. Pointer Register Byte
P7 P6 P5 P4 P3 P2 P1 P0
0 0 0 0 0 0 Register Bits
Table 2. Pointer Addresses
P1 P0
REGISTER
0 0 Temperature Register (Read Only)
0 1 Configuration Register (Read/Write)
10
11
TLOW Register (Read/Write)
THIGH Register (Read/Write)
Submit Documentation Feedback
5
5 Page 
TMP102
www.ti.com
SMBus ALERT FUNCTION
The TMP102 supports the SMBus Alert function.
When the TMP102 operates in Interrupt mode (TM =
'1'), the ALERT pin may be connected as an SMBus
Alert signal. When a master senses that an ALERT
condition is present on the ALERT line, the master
sends an SMBus Alert command (00011001) to the
bus. If the ALERT pin is active, the device
acknowledges the SMBus Alert command and
responds by returning its slave address on the SDA
line. The eighth bit (LSB) of the slave address byte
indicates if the ALERT condition was caused by the
temperature exceeding THIGH or falling below TLOW.
For POL = '0', this bit is low if the temperature is
greater than or equal to THIGH; this bit is high if the
temperature is less than TLOW. The polarity of this bit
is inverted if POL = '1'. Refer to Figure 15 for details
of this sequence.
If multiple devices on the bus respond to the SMBus
Alert command, arbitration during the slave address
portion of the SMBus Alert command determines
which device will clear its ALERT status. The device
with the lowest two-wire address wins the arbitration.
If the TMP102 wins the arbitration, its ALERT pin
becomes inactive at the completion of the SMBus
Alert command. If the TMP102 loses the arbitration,
its ALERT pin remains active.
GENERAL CALL
The TMP102 responds to a two-wire General Call
address (0000000) if the eighth bit is '0'. The device
acknowledges the General Call address and
responds to commands in the second byte. If the
second byte is 00000110, the TMP102 internal
registers are reset to power-up values. The TMP102
does not support the General Address acquire
command.
SBOS397 – AUGUST 2007
HIGH-SPEED (Hs) MODE
In order for the two-wire bus to operate at
frequencies above 400kHz, the master device must
issue an Hs-mode master code (00001xxx) as the
first byte after a START condition to switch the bus
to high-speed operation. The TMP102 does not
acknowledge this byte, but switches its input filters
on SDA and SCL and its output filters on SDA to
operate in Hs-mode, allowing transfers at up to
3.4MHz. After the Hs-mode master code has been
issued, the master transmits a two-wire slave
address to initiate a data transfer operation. The bus
continues to operate in Hs-mode until a STOP
condition occurs on the bus. Upon receiving the
STOP condition, the TMP102 switches the input and
output filters back to fast-mode operation.
TIMEOUT FUNCTION
The TMP102 resets the serial interface if SCL is held
low for 30ms (typ). The TMP102 releases the bus if it
is pulled low and waits for a START condition. To
avoid activating the timeout function, it is necessary
to maintain a communication speed of at least 1kHz
for SCL operating frequency.
NOISE
The TMP102 is a very low-power device and
generates very low noise on the supply bus.
Applying an RC filter to the V+ pin of the TMP102
can further reduce any noise the TMP102 might
propagate to other components. RF in Figure 11
should be less than 5kΩ and CF should be greater
than 10nF.
Supply Voltage
TMP102
SCL SDA
GND
V+
ALERT ADD0
RF £ 5kW
CF ³ 10nF
Figure 11. Noise Reduction
Submit Documentation Feedback
11
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet TMP102.PDF ] | |
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