PDF KLI-2113 Data sheet ( Hoja de datos )

Número de pieza	KLI-2113
Descripción	Linear CCD Image Sensor
Fabricantes	ON Semiconductor
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No Preview Available ! KLI-2113 Linear CCD Image Sensor Description The KLI−2113 Image Sensor is a high dynamic range, multispectral, linear CCD image sensor ideally suited for demanding color scanner applications. The imager consists of three parallel 2098-element photodiode arrays − one for each primary color. The KLI−2113 sensor offers high sensitivity, a high data rate, low noise, and negligible lag. Independent exposure control for each channel allows color balancing at the front end. CMOS-compatible 5 V clocks, and single 12 V DC supply are all that are required to drive the KLI−2113 sensor, simplifying the design of interface electronics. Table 1. GENERAL SPECIFICATIONS Parameter Typical Value Architecture 3 Channel, RGB Tri-linear CCD Pixels Count 2098 × 3 Pixel Size 14 mm (H) × 14 mm (V) Pixel Pitch 14 mm Inter-Array Spacing 112 mm (8 Lines Effective) Active Image Size 29.37 mm (H) × 0.24 mm (V) 29.4 mm (Diagonal) Saturation Signal 170,000 e− Dynamic Range 76 dB Responsivity (Wavelength) R, G, B (−RAA) R, G, B (−DAA)* Mono (−AAA, −AAB) Output Sensitivity 62, 42, 37 V/mJ/cm2 60, 40, 36 V/mJ/cm2 66 V/mJ/cm2 11.5 mV/e− Dark Current 0.02 pA/Pixel Dark Current Doubling Rate 9°C Charge Transfer Efficiency 0.99999/Transfer Photoresponse Non-Uniformity 5% Peak-Peak Lag (First Field) 0.6% Maximum Data Rate 20 MHz/Channel Package CERDIP (Sidebrazed, CuW) Cover Glass AR Coated, 2 Sides * Configuration KLI-2113-DAA uses Gen1 color filter set and is not recommended for new designs. NOTE: Parameters above are specified at T = 25°C and 2 MHz clock rates unless otherwise noted. www.onsemi.com Figure 1. KLI−2113 Linear CCD Image Sensor Features • High Resolution • Wide Dynamic Range • High Sensitivity • High Operating Speed • High Charge Transfer Efficiency • No Image Lag • Electronic Exposure Control • Pixel Summing Capability • Up to 2.0 V Peak-Peak Output • 5.0 V Clock Inputs • Two-Phase Register Clocking • On-Chip Dark Reference Applications • Digitization • Machine Vision • Mapping/Aerial • Photography ORDERING INFORMATION See detailed ordering and shipping information on page 2 of this data sheet. © Semiconductor Components Industries, LLC, 2015 November, 2015 − Rev. 5 1 Publication Order Number: KLI−2113/D 1 page Physical Description Pin Description and Device Orientation KLI−2113 VIDR SUB RD fR LOGR LOGG SUB 1 2 3 4 5 6 7 28 VIDG 27 SUB 26 VDD 25 VIDB 24 SUB 23 N/C 22 LOGB N/C 8 LS 9 IG 10 TG2 11 N/C 12 f2s 13 f2 14 21 N/C 20 N/C 19 ID 18 TG1 17 N/C 16 N/C 15 f1 Figure 3. KLI−2113 Pinout Table 4. PACKAGE PIN DESCRIPTION Pin Name Description 1 VIDR Red Output Video 2 SUB Substrate 3 RD Reset Drain 4 fR Reset Clock 5 LOGR Red Overflow Gate 6 LOGG Green Overflow Gate 7 SUB Substrate 8 N/C No Connection 9 LS Light Shield/Exposure Drain 10 IG Input Gate/LOG Test Pin 11 TG2 Outer Transfer Gate 12 N/C No Connection 13 f2s Phase2 Shift Register Summing Gate Clock 14 f2 Phase2 Shift Register Clock Pin Name Description 15 f1 Phase1 Shift Register Clock 16 N/C No Connection 17 N/C No Connection 18 TG1 Inner Transfer Gate 19 ID Input Diode Test Pin 20 N/C No Connection 21 N/C No Connection 22 LOGB Blue Overflow Gate 23 N/C No Connection 24 SUB Substrate 25 VIDB Blue Output Video 26 VDD Amplifier Supply 27 SUB Substrate 28 VIDG Green Output Video www.onsemi.com 5 5 Page KLI−2113 AC Operating Conditions Table 9. CLOCK LEVELS Description Symbol Minimum CCD Readout Clocks High Vf1H, Vf2H, Vf2sH CCD Readout Clocks Low Vf1L, Vf2L, Vf2sL Transfer Clocks High VTG1H, VTG2H Transfer Clocks Low VTG1L, VTG2L Reset Clock High VfRH Reset Clock Low VfRL Exposure Clocks High VLOG1H, VLOG2H Exposure Clocks Low VLOG1L, VLOG2L 1. Tie pin to 0 V for applications where exposure control is not used. 4.75 −0.1 4.75 −0.1 4.75 −0.1 4.75 −0.1 Nominal 5.0 0.0 5.0 0.0 5.0 0.0 5.0 0.0 Maximum 5.25 0.1 5.25 0.1 5.25 0.1 5.25 0.1 Table 10. AC TIMING LEVELS Description Symbol CCD Element Duration 1e- (= 1/fCLK) Line/Integration Period 1L (= tINT) PD−CCD Transfer Period tPD Transfer Gate 1 Clear tTG1 Transfer Gate 2 Clear tTG2 LOGGate Duration tLOG1 LOGGate Clear tLOG2 Reset Pulse Duration tRST Clamp to f2 Delay tCD Sample to Reset Edge Delay tSD CCD Clock Rise Time tR 1. Recommended delays for Correlated Double Sampling of output. Minimum 50 0.108 1.0 500 500 1 1 9 5 5 − Nominal 50 1.066 − − − − − − − − 30 Maximum − − − − − − − − − − − Units V V V V V V V V Units ns ms ms ns ns ms ms ns ns ns ns Notes 1 1 Notes 1 1 Typical www.onsemi.com 11 11 Page

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