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PDF AR0134CS Data sheet ( Hoja de datos )
| Número de pieza | AR0134CS | |
| Descripción | 1/3-Inch 1.2 Mp CMOS Digital Image Sensor | |
| Fabricantes | ON Semiconductor | |
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AR0134CS: 1/3-Inch 1.2 Mp CMOS Digital Image Sensor
Features
1/3-Inch 1.2 Mp CMOS Digital Image Sensor with
Global Shutter
AR0134CS Datasheet, Rev. 8
For the latest datasheet revision, please visit www.onsemi.com
Features
• ON Semiconductor's 3rd Generation Global Shutter
Technology
• Superior low-light performance
• HD video (720p60)
• Video/Single Frame mode
• Flexible row-skip modes
• On-chip AE and statistics engine
• Parallel and serial output
• Support for external LED or flash
• Auto black level calibration
• Context switching
Applications
• Scene processing
• Scanning and machine vision
• 720p60 video applications
General Description
ON Semiconductor's AR0134 is a 1/3-inch 1.2 Mp
CMOS digital image sensor with an active-pixel array
of 1280H x 960V. It is designed for low light perfor-
mance and features a global shutter for accurate cap-
ture of moving scenes. It includes sophisticated
camera functions such as auto exposure control, win-
dowing, scaling, row skip mode, and both video and
single frame modes. It is programmable through a sim-
ple two-wire serial interface. The AR0134 produces
extraordinarily clear, sharp digital pictures, and its
ability to capture both continuous video and single
frames makes it the perfect choice for a wide range of
applications, including scanning and industrial
inspection.
Table 1:
Key Parameters
Parameter
Typical Value
Optical format
1/3-inch (6 mm)
Active pixels
1280H x 960V = 1.2 Mp
Pixel size
3.75 m
Color filter array
RGB Bayer or Monochrome
Shutter type
Global shutter
Input clock range
6 – 50 MHz
Output pixel clock (maximum) 74.25 MHz
Output
Serial
Parallel
HiSPi
12-bit
Frame rate
Full resolution 54 fps
720p
60 fps
Responsivity
Monochrome 6.1 V/lux-sec
Color
5.3 V/lux-sec
SNRMAX
Dynamic range
38.6 dB
64 dB
I/O 1.8 or 2.8 V
Supply
voltage
Digital
Analog
1.8 V
2.8 V
HiSPi
0.4 V
Power consumption
<400 mW
Operating temperature
–30°C to +70°C (ambient)
–30°C to +80°C (junction)
9 x 9 mm 64-pin iBGA
Package options
10 x 10 mm 48-pin iLCC
Bare die
AR0134CS/D Rev. 8, Pub. 1/16 EN
1 ©Semiconductor Components Industries, LLC 2016,
1 page  
AR0134CS: 1/3-Inch 1.2 Mp CMOS Digital Image Sensor
Features Overview
processing signal chain (which provides further data path corrections and applies digital
gain). The pixel data are output at a rate of up to 74.25 Mp/s, in parallel to frame and line
synchronization signals.
Features Overview
The AR0134 Global Sensor shutter has a wide array of features to enhance functionality
and to increase versatility. A summary of features follows. Please refer to the AR0134
Developer Guide for detailed feature descriptions, register settings, and tuning guide-
lines and recommendations.
• Operating Modes
The AR0134 works in master (video), trigger (single frame), or Auto Trigger modes. In
master mode, the sensor generates the integration and readout timing. In trigger
mode, it accepts an external trigger to start exposure, then generates the exposure and
readout timing. The exposure time is programmed through the two-wire serial inter-
face for both modes. Trigger mode is not compatible with the HiSPi interface.
• Window Control
Configurable window size and blanking times allow a wide range of resolutions and
frame rates. Digital binning and skipping modes are supported, as are vertical and
horizontal mirror operations.
• Context Switching
Context switching may be used to rapidly switch between two sets of register values.
Refer to the AR0134 Developer Guide for a complete set of context switchable regis-
ters.
• Gain
The AR0134 Global Shutter sensor can be configured for analog gain of up to 8x, and
digital gain of up to 8x.
• Automatic Exposure Control
The integrated automatic exposure control may be used to ensure optimal settings of
exposure and gain are computed and updated every other frame. Refer to the AR0134
Developer Guide for more details.
• HiSPi
The AR0134 Global Shutter image sensor supports two or three lanes of Streaming-SP
or Packetized-SP protocols of ON Semiconductor's High-Speed Serial Pixel Interface.
• PLL
An on chip PLL provides reference clock flexibility and supports spread spectrum
sources for improved EMI performance.
• Reset
The AR0134 may be reset by a register write, or by a dedicated input pin.
• Output Enable
The AR0134 output pins may be tri-stated using a dedicated output enable pin.
• Temperature Sensor
The temperature sensor is only guaranteed to be functional when the AR0134 is
initially powered-up or is reset at temperatures at or above 0°C.
• Black Level Correction
• Row Noise Correction
• Column Correction
• Test Patterns
Several test patterns may be enabled for debug purposes. These include a solid color,
color bar, fade to grey, and a walking 1s test pattern.
AR0134CS/D Rev. 8, Pub. 1/16 EN
5 ©Semiconductor Components Industries, LLC,2016.
5 Page 
AR0134CS: 1/3-Inch 1.2 Mp CMOS Digital Image Sensor
Configuration and Pinout
Table 3: Pin Descriptions - 63-Ball iBGA Package
Name
SLVS0_N
SLVS0_P
SLVS1_N
SLVS1_P
STANDBY
VDD_PLL
SLVSC_N
SLVSC_P
SLVS2_N
SLVS2_P
VAA
EXTCLK
VDD_SLVS
SLVS3_N
SLVS3_P
DGND
VDD
AGND
SADDR
SCLK
SDATA
VAA_PIX
LINE_VALID
FRAME_VALID
PIXCLK
FLASH
VDD_IO
DOUT8
DOUT9
DOUT10
DOUT11
TEST
DOUT4
DOUT5
DOUT6
DOUT7
TRIGGER
OE_BAR
DOUT0
DOUT1
DOUT2
DOUT3
iBGA Pin
A2
A3
A4
A5
A8
B1
B2
B3
B4
B5
B7, B8
C1
C2
C3
C4
C5, D4, D5, E5, F5, G5, H5
A6, A7, B6, C6, D6
C7, C8
D1
D2
D3
D7, D8
E1
E2
E3
E4
E6, F6, G6, H6, H7
F1
F2
F3
F4
F7
G1
G2
G3
G4
G7
Type
Output
Output
Output
Output
Input
Power
Output
Output
Output
Output
Power
Input
Power
Output
Output
Power
Power
Power
Input
Input
I/O
Power
Output
Output
Output
Output
Power
Output
Output
Output
Output
Input
Output
Output
Output
Output
Input
G8 Input
H1 Output
H2 Output
H3 Output
H4 Output
Description
HiSPi serial data, lane 0, differential N.
HiSPi serial data, lane 0, differential P.
HiSPi serial data, lane 1, differential N.
HiSPi serial data, lane 1, differential P.
Standby-mode enable pin (active HIGH).
PLL power.
HiSPi serial DDR clock differential N.
HiSPi serial DDR clock differential P.
HiSPi serial data, lane 2, differential N.
HiSPi serial data, lane 2, differential P.
Analog power.
External input clock.
HiSPi power. (May leave unconnected if parallel interface is used)
(Unsupported) HiSPi serial data, lane 3, differential N.
(Unsupported) HiSPi serial data, lane 3, differential P.
Digital GND.
Digital power.
Analog GND.
Two-Wire Serial address select.
Two-Wire Serial clock input.
Two-Wire Serial data I/O.
Pixel power.
Asserted when DOUT line data is valid.
Asserted when DOUT frame data is valid.
Pixel clock out. DOUT is valid on rising edge of this clock.
Control signal to drive external light sources.
I/O supply power.
Parallel pixel data output.
Parallel pixel data output.
Parallel pixel data output.
Parallel pixel data output (MSB)
Manufacturing test enable pin (connect to DGND).
Parallel pixel data output.
Parallel pixel data output.
Parallel pixel data output.
Parallel pixel data output.
Exposure synchronization input. (Connect to DGND if HiSPi interface is
used)
Output enable (active LOW).
Parallel pixel data output (LSB)
Parallel pixel data output.
Parallel pixel data output.
Parallel pixel data output.
AR0134CS/D Rev. 8, Pub. 1/16 EN
11
©Semiconductor Components Industries, LLC,2016.
11 Page | ||
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