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PDF TJ2996 Data sheet ( Hoja de datos )
| Número de pieza | TJ2996 | |
| Descripción | DDR Termination Regulator | |
| Fabricantes | HTC Korea | |
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DDR Termination Regulator
TJ2996
FEATURES
z Source and sink current
z Low output voltage offset
z No external resistors required
z Linear topology
z Suspend to Ram (STR) functionality
z Low external component count
z Thermal Shutdown
z Available in SOP8, SOP8-PP Packages
APPLICATION
z DDR-I, DDR-II and DDR-Ⅲ Termination Voltage
z SSTL-2 and SSTL-3 Termination
z HSTL Termination
SOP8 / SOP8-PP PKG
ORDERING INFORMATION
Device
TJ2996D
TJ2996DP
Package
SOP8
SOP8-PP
DESCRIPSION
The TJ2996 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for
termination of DDR-SDRAM. The device contains a high-speed operational amplifier to provide excellent
response to load transients. The output stage prevents shoot through while delivering 1.5A continuous
current and transient peaks up to 3A in the application as required for DDR-SDRAM termination. The
TJ2996 also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference
for the chipset and DIMMs. An additional feature found on the TJ2996 is an active low shutdown ( ) pin
that provides Suspend To RAM (STR) functionality. When is pulled low the VTT output will tri-state
providing a high impedance output, but, VREF will remain active. A power savings advantage can be obtained
in this mode through lower quiescent current.
Absolute Maximum Ratings
CHARACTERISTIC
Supply Voltage to GND
Lead Temperature (Soldering, 10 sec)
Storage Temperature Range
Operating Junction Temperature Range
Recommended Operation Range
CHARACTERISTIC
AVIN to GND
PVIN & SDVIN to GND
Ordering Information
SYMBOL
PVIN
AVIN
VDDQ
TSOL
TSTG
TJOPR
MIN.
-0.3
-0.3
-0.3
-65
-40
SYMBOL
AVIN
PVIN & SD Input
MIN.
2.3
0
MAX.
6.0
6.0
6.0
260
150
125
UNIT
V
℃
℃
℃
MAX.
5.5
AVIN
UNIT
V
V
Package
SOP8
SOP8-PP
Order No.
TJ2996D
TJ2996DP
Description
DDR Termination Regulator
DDR Termination Regulator
Package Marking
TJ2996
TJ2996
Reel
Reel
Supplied As
Jul. 2010 - Rev. 1.5.3
1/14
HTC
Free Datasheet http://www.datasheet4u.com/
1 page  
DDR Termination Regulator
TJ2996
AVIN : 2.0V/div, VDDQ/PVIN : 2.0V/div, VTT : 500mV/div, IOUT : 1A/div, Time : 10ms/div
Load (0A → 1A)
AVIN : 2.0V/div, VDDQ/PVIN : 2.0V/div, VTT : 500mV/div, IOUT : 1A/div, Time : 10ms/div
Load (1A → 0A)
VDDQ = 1.8V
AVIN vs. Quiescent Current
Jul. 2010 - Rev. 1.5.3
5/14 HTC
Free Datasheet http://www.datasheet4u.com/
5 Page 
DDR Termination Regulator
TJ2996
FIGURE 4. SSTL-2 Implementation with higher voltage rails
DDR-II APPLICATIONS
With the separate VDDQ pin and an internal resistor divider it is possible to use the TJ2996 in
applications utilizing DDR-II memory. Figure 3 and Figure 4 show several implementations of
recommended circuits. Figure 3 shows the recommended circuit configuration for DDR-II applications.
The output stage is connected to the 1.8V rail and the AVIN pin can be connected to either a 3.3V or 5V
rail.
FIGURE 5. Recommended DDR-II Termination
If it is not desirable to use the 1.8V rail it is possible to connect the output stage to a 3.3V rail. Care
should be taken to do not exceed the maximum junction temperature as the thermal dissipation
increases with lower VTT output voltages. For this reason it is not recommended to power PVIN off a rail
higher than the nominal 3.3V. The advantage of this configuration is that it has the ability to source and
sink a higher maximum continuous current.
Jul. 2010 - Rev. 1.5.3
FIGURE 6. DDR-II Termination with higher voltage rails
11/14
HTC
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet TJ2996.PDF ] | |
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