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PDF A8292 Data sheet ( Hoja de datos )
| Número de pieza | A8292 | |
| Descripción | Dual LNB Supply and Control Voltage Regulator | |
| Fabricantes | Allegro MicroSystems | |
| Logotipo |  |
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A8292
Dual LNB Supply and Control Voltage Regulator
Features and Benefits
Description
▪ 2-wire serial I2C™ -compatible interface: control (write) and Intended for analog and digital satellite receivers, this dual
status (read)
low-noise block converter regulator (LNBR) is a monolithic
▪ LNB voltages (16 programmable levels) compatible with linear and switching voltage regulator, specifically designed to
all common standards
provide the power and the interface signals to two LNB down
▪ Tracking switch-mode power converter for lowest dissipation converters via coaxial cables. TheA8292 requires few external
▪ Integrated converter switches and current sensing
components, with the boost switches and compensation circuitry
▪ Provides up to 500 mA per channel and 750 mA total
integrated inside of the device. A high switching frequency is
▪ Static current limit circuit allows full current at startup and chosen to minimize the size of the passive filtering components,
13→18V output transition; reliably starts wide load range further assisting in cost reduction. The high level of component
▪ Push-pull output stage minimizes 13→18V and 18→13V
integration ensures extremely low noise and ripple figures.
output transition times for highly capacitive loads
▪ Adjustable rise/fall time via external timing capacitor
▪ Built-in tone oscillator, factory-trimmed to 22 kHz
facilitates DiSEqC™ tone encoding, even at no-load
▪ Four methods of 22 kHz tone generation, via I2C™ data
bits and/or external pin
The A8292 has been designed for high efficiency, utilizing
the Allegro® advanced BCD process. The integrated boost
switches have been optimized to minimize both switching and
static losses. To further enhance efficiency, the voltage drop
across the tracking regulators has been minimized.
▪ 22 kHz tone detector facilitates DiSEqC™ 2.0 decoding The A8292 has integrated tone detection capability, to support
▪ Auxiliary modulation input
full two-way DiSEqC™ communications. Several schemes
▪ LNB overcurrent with timer
are available for generating tone signals, all the way down
▪ Diagnostics for output voltage level, input supply UVLO, to no-load, and using either the internal clock or an external
and DiSEqC™ tone output
▪ Cable disconnect diagnostic
timewww.DataSheet4U.com source.
Package:
28 pin 5 mm × 5mm MLP/QFN
(suffix ET)
Continued on the next page…
Functional Block Diagram
VS
VDD
C2
100 μF
A
Channel 1
L1
33 μH
L3
D1 1 MH
A8292
VIN
C1
100 nF
VREG
C3
220 nF
Regulator
R3
R2
R1
SDA
SCL
I2 C–
Compatible
Interface
IRQ
C5
100 μF
C6
1 μF
R4 R5
C4
100 nF
TDO1 EXTM1 LX1
GNDLX1 BOOST1 VCP1
Boost
Converter
Charge
Pump
C12 D
TMode1
EXTM1
Fsw
DAC
LNB
Voltage
Control
Wave
Shape
TCAP1
TGate1
Fault Monitor
OCP1
OCP2
PNG1
PNG2
TSD
VUV
Fsw
Clock
Divider 22 kHz
Oscillator
PAD
GND
VPump
Linear
Stage
TDO1
Tone
Detect
R6
15 7
LNB1
C8
D2 220 nF
L2
220 μH
R8
30 7
C9
220 nF
D
TCAP1
C7
10 nF
C11
0.68 μF
B
TDI1
R7
100 7
C10
10 nF
C13
10 nF
D3
C
VOUT1
D4
C
A Channel 1 of 2 channels shown.
B R8-C11 network is needed only when high
inductive load is applied, such as ProBrand LNB.
C D3 and D4 are used for surge protection.
D Either C12 or C9 should be used, but not both.
8292-DS, Rev. 3
1 page  
A8292
Dual LNB Supply and Control Voltage Regulator
ELECTRICAL CHARACTERISTICS (continued) at TA = 25°C, VIN = 8 to 16 V, unless noted otherwise1
Characteristics
Symbol
Test Conditions
Min.
Tone
Tone Frequency
fTONE
20
Tone Amplitude, Peak-to-Peak
VTONE(pp) ILOAD = 0 to 450 mA, CLOAD = 750 nF
400
Tone Duty Cycle
Tone Rise Time
Tone Fall Time
EXTM Logic Input
EXTM Input Leakage
Tone Detector
Tone Detect Input Amplitude Receive, Peak-to-
Peak
Tone Detect Input Amplitude Transmit, Peak-
to-Peak
Tone Reject Input Amplitude, Peak-to-Peak
Frequency Capture
Input Impedance2
TDO Output Voltage
TDO Output Leakage
I2C™-Compatible Interface
Logic Input (SDA,SCL) Low Level
Logic Input (SDA,SCL) High Level
Logic Input Hysteresis
Logic Input Current
Logic Output Voltage SDA and IRQ
Logic Output Leakage SDA and IRQ
SCL Clock Frequency
Output Fall Time
Bus Free Time Between Stop/Start
Hold Time Start Condition
Setup Time for Start Condition
SCL Low Time
SCL High Time
Data Setup Time
Data Hold Time
Setup Time for Stop Condition
DCTONE
trTONE
tfTONE
VEXTM(H)
VEXTM(L)
IEXTMLKG
ILOAD = 0 to 450 mA, CLOAD = 750 nF
ILOAD = 0 to 450 mA, CLOAD = 750 nF
ILOAD = 0 to 450 mA, CLOAD = 750 nF
40
5
5
2.0
–
–1
VTDR(pp) fTONE = 22 kHz sine wave, TMODE = 0
VTDT(pp)Int
VTDT(pp)Ext
VTRI(pp)
fTDI
ZTDI
VTDO(L)
ITDOLKG
fTONE = 22 kHz sine wave, using internal tone
(options 1 and 2, in figure 1)
fTONE = 22 kHz sine wave, using external
tone (options 3 and 4, in figure 1)
fTONE = 22 kHz sine wave
600 mVpp sine wave
Tone present, ILOAD = 3 mA
Tone absent, VTDO = 7 V
300
400
300
–
17.6
–
–
–
VSCL(L)
VSCL(H)
VI2CIHYS
II2CI
Vt2COut(L)
Vt2CLKG
fCLK
tfI2COut
tBUF
tHD:STA
tSU:STA
tLOW
tHIGH
tSU:DAT
tHD:DAT
tSU:STO
VI2CI = 0 to 7 V
ILOAD = 3 mA
Vt2COut = 0 to 7 V
Vt2COut(H) to Vt2COut(L)
–
2.0
–
–10
–
–
–
–
1.3
0.6
0.6
1.3
0.6
100
0
0.6
Typ. Max. Units
22 24 kHz
620 800 mV
50 60 %
10 15 μs
10 15 μs
––V
– 0.8 V
– 1 μA
– – mV
– – mV
– – mV
– 100 mV
– 26.4 kHz
8.6 – kΩ
– 0.4 V
– 10 μA
–
–
150
<±1.0
–
–
–
–
–
–
–
–
–
–
–
–
0.8
–
–
10
0.4
10
400
250
–
–
–
–
–
–
900
–
V
V
mV
μA
V
μA
kHz
ns
μs
μs
μs
μs
μs
ns
ns
μs
Continued on the next page…
Allegro MicroSystems, Inc.
5
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
5 Page 
A8292
Dual LNB Supply and Control Voltage Regulator
The OCP (with ODT= 0), DIS, PNG, CAD and TDET status
bits do not cause an interrupt. All these bits are continually updat-
ed, apart from the DIS bit, which changes when the LNB is either
disabled, intentionally or due to a fault, or is enabled.
When the master recognizes an interrupt, it addresses all slaves
connected to the interrupt line in sequence, and then reads the sta-
tus register to determine which device is requesting attention. The
A8292 latches all conditions in the Status register until the comple-
tion of the data read. The action at the resampling point is further
defined in the Status Register section. The bits in the Status
register are defined such that the all-zero condition indicates that
the A8292 is fully active with no fault conditions.
When VIN is initially applied, the I2C™-compatible interface
does not respond to any requests until the internal logic supply
VREG has reached its operating level. Once VREG has reached this
point, the IRQ output goes active, and the VUV bit is set. After the
A8292 acknowledges the address, the IRQ flag is reset. After the
master reads the status registers, the registers are updated with the
VUV reset.
Allegro MicroSystems, Inc.
11
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet A8292.PDF ] | |
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