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AD6122 반도체 회로 부품 판매점

CDMA 3 V Transmitter IF Subsystem with Integrated Voltage Regulator



Analog Devices 로고
Analog Devices
AD6122 데이터시트, 핀배열, 회로
a
CDMA 3 V Transmitter IF Subsystem
with Integrated Voltage Regulator
AD6122
FEATURES
Fully Compliant with IS98A and PCS Specifications
Linear IF Amplifier
–63 dB to +34 dB
Linear-in-dB Gain Control
Temperature-Compensated Gain Control
Quadrature Modulator
Modulates IFs from 50 MHz to 350 MHz
Integral Low Dropout Regulator
Accepts 2.9 V to 4.2 V Input from Battery
Low Power
10.4 mA at Midgain
<10 A Sleep Mode Operation
Companion Receiver IF Chip Available (AD6121)
APPLICATIONS
CDMA, W-CDMA, AMPS and TACS Operation
QPSK Transmitters
GENERAL DESCRIPTION
The AD6122 is a low power IF transmitter subsystem, specifi-
cally designed for CDMA applications. It consists of an I and Q
modulator, a divide-by-two quadrature generator, high dynamic
range IF amplifiers with voltage-controlled gain and a power-
down control input. An integral low dropout regulator allows
operation from battery voltages from 2.9 V to 4.2 V.
The gain control input accepts an external gain control voltage
input from a DAC. It provides 97 dB of gain control with a
nominal 75 dB/V scale factor. Either an internal or an external
reference may be used to set the gain-control scale factor.
The I and Q modulator accepts differential quadrature base-
band inputs from a CDMA baseband converter. The local oscil-
lator is injected at twice the IF frequency. A divide-by-two
quadrature generator followed by dual polyphase filters ensures
± 1° quadrature accuracy.
The modulator provides a common-mode reference output to
bias the transmit DACs in the baseband converter to the same
common-mode voltage as the modulator inputs, allowing dc
coupling between the two ICs and thus eliminating the need to
charge and discharge coupling capacitors. This allows the fastest
power-up and power-down times for the AD6122 and CDMA
baseband ICs.
The AD6122 is fabricated using a 25 GHz ft silicon BiCMOS
process and is packaged in a 28-lead SSOP and a 32-leadless
LPCC chip scale package (5 mm × 5 mm).
FUNCTIONAL BLOCK DIAGRAM
VCC
QUADRATURE
MODULATOR
OUTPUT
I INPUT
LOCAL
OSCILLATOR
INPUT
QUADRATURE MODULATOR
،2
Q INPUT
COMMON-MODE
REFERENCE
OUTPUT
VPOS
LOW
VREG
DROPOUT
REGULATOR
ATTENUATOR
AD6122
GAIN
CONTROL
SCALE
FACTOR
IF AMPLIFIER
INPUT
IF AMPLIFIERS
TRANSMIT
OUTPUT
TEMPERATURE
COMPENSATION
POWER- POWER-
DOWN 1 DOWN 2
1.23 V
REFERENCE
GAIN CONTROL
REFERENCE
OUTPUT
VOLTAGE
INPUT
GAIN CONTROL
VOLTAGE
INPUT
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000


AD6122 데이터시트, 핀배열, 회로
AD6122–SPECIFICATIONS (TA = +25؇C, VCC = +3.0 V, LO = 2 ؋ IF, REFIN = 1.23 V, LDO Enabled, unless otherwise
noted) NOTE: All powers shown in dBm are referred to 1 k.
Specification
Conditions
Min Typ
Max Unit
MODULATOR
Output Level
Output Third Order Harmonic
I/Q Inputs
Differential Input Voltage
Bandwidth
Resistance
Quadrature Accuracy
Amplitude Balance
Output Referred Noise
Modulator Common-Mode Reference
LO Input Resistance
LO Input Capacitance
LO Carrier Leakage
LO = 260.76 MHz (2 × IF), 100 mV p-p
500 mV p-p Differential I and Q Inputs;
Output Level Referred to a 1 kDifferential Load
Differential
–3 dB
0.9 MHz to 5.0 MHz Offsets
Differential Input at 260.38 MHz
Differential Input at 260.38 MHz
Bias I/Q Using MODCMREF
–21
–50
500
20
30
±1
± 0.1
–169
1.408
1.2
2.4
–40
dBm
dBc
mV p-p
MHz
k
°
dB
dBm/Hz
V
k
pF
dBc
IF AMPLIFIER
Noise Figure
Input 1 dB Compression Point
Input Third-Order Intercept
Gain Flatness
Input Capacitance
Differential IF Input Resistance
Differential IF Output Resistance
Differential IF Output Capacitance
FIF = 130.38 MHz
VGAIN = 2.5 V, 1 kDifferential Load
VGAIN = 2.5 V
VGAIN = 2.5 V
IF ± 630 kHz
Shunt Equivalent Model at 130.38 MHz
Shunt Equivalent Model at 130.38 MHz
Per Pin at 130.38 MHz
Per Pin at 130.38 MHz
10
–32
–24
± 0.25
2.3
680
4.2
2.0
dB
dBm
dBm
dB
pF
k
pF
GAIN CONTROL INTERFACE
Gain Scaling
Gain Scaling Linearity
Minimum Gain
Maximum Gain
Gain Control Response Time
Input Resistance at REFIN
Input Resistance at VGAIN
Using Internal Reference
For a Typical Dynamic Range of 92 dB
VGAIN = 0.5 V
VGAIN = 2.5 V
90 dB Gain Change, Min Gain to Max Gain
75 dB/V
± 3 dB/V
–63 dB
+34 dB
0.7 µs
10 M
109 k
POWER-DOWN INTERFACE
Logic Threshold High
Logic Threshold Low
Input Current for Logical High
Turn-On Response Time
Turn-Off Response Time
Power-Up on Logical High
Measure to Settling of AGC from Standby Mode
To 200 µA Supply Current
1.34 V
1.30 V
0.1 µA
23 µs
187 ns
LOW DROPOUT REGULATOR
Input Range
Nominal Output
Dropout Voltage
Reference Output
External PNP Pass Transistor, VCESAT = –0.4 V
Max, hFE = 100/300 Min/Max
2.9–4.2
2.70
200
1.23
V
V
mV
V
POWER SUPPLY
Supply Range Bypassing Internal LDO
Supply Current
Standby Current
VGAIN = 1.5 V (Unity Gain)
2.7–5.0
10.4
7.8
V
mA
µA
OPERATING TEMPERATURE
TMIN to TMAX
Specifications subject to change without notice.
–40 +85 °C
–2– REV. B




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CDMA 3 V Receiver IF Subsystem with Integrated Voltage Regulator - Analog Devices



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CDMA 3 V Transmitter IF Subsystem with Integrated Voltage Regulator - Analog Devices