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NPIC6C595 반도체 회로 부품 판매점

Power logic 8-bit shift register



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NXP Semiconductors
NPIC6C595 데이터시트, 핀배열, 회로
NPIC6C595
Power logic 8-bit shift register; open-drain outputs
Rev. 1 — 20 August 2012
Product data sheet
1. General description
The NPIC6C595 is an 8-bit serial-in/serial or parallel-out shift register with a storage
register and open-drain outputs. Both the shift and storage register have separate clocks.
The device features a serial input (DS) and a serial output (Q7S) to enable cascading and
an asynchronous reset input (MR). A LOW on MR resets both the shift register and
storage register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The
data in the shift register is transferred to the storage register on a LOW-to-HIGH transition
of the STCP input and to the Q7S output on a LOW-to-HIGH transition of the SHCP input.
If both clocks are connected together, the shift register is always one clock pulse ahead of
the storage register. Data in the storage register drives the gate of the output
extended-drain NMOS transistor whenever the output enable input (OE) is LOW. A HIGH
on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE
input does not affect the state of the registers. The open-drain outputs are 33 V/100 mA
continuous current extended-drain NMOS transistors designed for use in systems that
require moderate load power such as LEDs. Integrated voltage clamps in the outputs
provide protection against inductive transients. This feature makes the device suitable for
power driver applications such as relay, solenoids and other low-current or
medium-voltage loads.
2. Features and benefits
Specified from 40 C to +125 C
Low RDSon
Eight Power EDNMOS transistor outputs of 100 mA continuous current
250 mA current limit capability
Output clamping voltage 33 V
30 mJ avalanche energy capability
All registers cleared with single input
Low power consumption
ESD protection:
HBM JDS-001 Class 2 exceeds 2500 V
CDM JESD22-C101E exceeds 1000 V
3. Applications
LED sign
Graphic status panel
Fault status indicator


NPIC6C595 데이터시트, 핀배열, 회로
NXP Semiconductors
NPIC6C595
Power logic 8-bit shift register; open-drain outputs
4. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
Description
Version
NPIC6C595D
40 C to +125 C SO16
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
NPIC6C595PW
40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; SOT403-1
body width 4.4 mm
NPIC6C595BQ
40 C to +125 C
DHVQFN16 plastic dual in-line compatible thermal enhanced SOT763-1
very thin quad flat package; no leads; 16 terminals;
body 2.5 3.5 0.85 mm
5. Functional diagram
15 10
SHCP
STCP
Q0
3
Q1 4
5
Q2
2
DS
6
Q3
Q4 11
Q5 12
13
Q6
14
Q7
Q7S 9
MR OE
78
aaa-002547
Fig 1. Logic symbol
VCC
2 DS
15 SHCP
7 MR
8-STAGE SHIFT REGISTER
10 STCP
8-BIT STORAGE REGISTER
Q7S 9
8 OE
OPEN-DRAIN OUTPUTS
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
3 4 5 6 11 12 13 14
aaa-002542
Fig 2. Functional diagram
Qn
33 V
GND
Fig 3. Schematic of all inputs
aaa-002550
GND
aaa-002551
Fig 4. Schematic of open-drain outputs (Qn)
NPIC6C595
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 20 August 2012
© NXP B.V. 2012. All rights reserved.
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