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PDF 74C165 Data sheet ( Hoja de datos )
| Número de pieza | 74C165 | |
| Descripción | Parallel-Load 8-Bit Shift Register | |
| Fabricantes | Fairchild | |
| Logotipo |  |
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October 1987
Revised May 2002
MM74C165
Parallel-Load 8-Bit Shift Register
General Description
The MM74C165 functions as an 8-bit parallel-load, serial
shift register. Data is loaded into the register independent
of the state of the clock(s) when PARALLEL LOAD (PL) is
low. Shifting is inhibited as long as PL is low. Data is
sequentially shifted from complementary outputs, Q7 and
Q7, highest-order bit (P7) first. New serial data may be
entered via the SERIAL DATA (Ds) input. Serial shifting
occurs on the rising edge of CLOCK1 or CLOCK2. Clock
inputs may be used separately or together for combined
clocking from independent sources. Either clock input may
be used also as an active-low clock enable. To prevent
double-clocking when a clock input is used as an enable,
the enable must be changed to a high level (disabled) only
while the clock is HIGH.
Features
s Wide supply voltage range: 3V to 15V
s Guaranteed noise margin: 1V
s High noise immunity: 0.45 VCC (typ.)
s Low power TTL compatibility: fan out of 2 driving 74L
s Parallel loading independent of clock
s Dual clock inputs
s Fully static operation
Ordering Code:
Order Number Package Number
Package Description
MM74165N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Connection Diagram
Top View
© 2002 Fairchild Semiconductor Corporation DS005897
www.fairchildsemi.com
1 page  
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| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet 74C165.PDF ] | |
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