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Arizona Microtek |
www.DataSheet4U.com
ARIZONA MICROTEK, INC.
AZ10E142
AZ100E142
ECL/PECL 9-bit Shift Register
FEATURES
PACKAGE AVAILABILITY
• 700 MHz Minimum Shift Frequency
PACKAGE PART NUMBER MARKING NOTES
• 9-Bit for Byte-Parity Application
• Asynchronous Master Reset
PLCC 28
AZ10E142FN
AZM10E142
<Date Code>
1,2
• Dual Clocks
• Operating Range of 4.2V to 5.46V
PLCC 28
AZ100E142FN
AZM100E142
<Date Code>
1,2
•
75kΩ Internal Input Pulldown Resistors
1
2
Add R2 at end of part number for 13 inch (2.5K parts) Tape & Reel.
Date code format: “YY” for year followed by “WW” for week.
• Direct Replacement for ON Semi
MC10E142 & MC100E142
DESCRIPTION
The AZ10/100E142 is a 9-bit shift register, designed with byte-parity applications in mind. The E142 performs
serial/parallel in and serial/parallel out, shifting in one direction. The nine inputs D0-D8 accept parallel input data,
while S-IN accepts serial input data. The Qn outputs do not need to be terminated for the shift operation to function.
To minimize noise and power, any Q output not used should be left unterminated.
The SEL (Select) input pin is used to switch between the two modes of operation – SHIFT and LOAD. The shift
direction is from bit 0 to bit 8. Input data is accepted by the registers a set-up time before the positive going edge of
CLK1 or CLK2; shifting is also accomplished on the positive clock edge. A HIGH on the Master Reset pin (MR)
asynchronously resets all the registers to zero.
NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.
SEL
25
MR 26
CLK1
27
D8
24
D7 D6
23 22
D5 VCCO
21 20
Q8
19
18
17
Q7
Q6
CLK2
28
VEE 1
S-IN 2
Pinout: 28-lead
PLCC (top view)
16 VCC
15 Q5
14 VCCO
D0 3
13 Q4
D1 4
12 Q3
5 6 7 8 9 10 11
D2
D3
D4 VCCO
Q0
Q1
Q2
1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (480) 890-2541
www.azmicrotek.com
AZ10E142
AZ100E142
FUNCTION TABLE
SEL MODE
L Load
H Shift
PIN DESCRIPTION
PIN
D0 – D8
S – IN
SEL
CLK1, CLK2
MR
Q0 – Q8
VCC , VCCO
VEE
FUNCTION
Parallel Data Inputs
Serial Data Input
Mode Select Input
Clock Inputs
Master Reset
Data Outputs
Positive Supply
Negative Supply
LOGIC SYMBOL
S-IN
D0
D1
D2
D3
D4
D5
D6
D7
D8
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
SEL
CLK1
CLK2
MR
Absolute Maximum Ratings are those values beyond which device life may be impaired.
Symbol
Characteristic
Rating
VCC PECL Power Supply (VEE = 0V)
VI PECL Input Voltage (VEE = 0V)
VEE ECL Power Supply (VCC = 0V)
VI ECL Input Voltage (VCC = 0V)
IOUT
Output Current
--- Continuous
--- Surge
0 to +8.0
0 to +6.0
-8.0 to 0
-6.0 to 0
50
100
TA Operating Temperature Range
TSTG Storage Temperature Range
-40 to +85
-65 to +150
Unit
Vdc
Vdc
Vdc
Vdc
mA
°C
°C
10K ECL DC Characteristics (VEE = -4.94V to -5.46V, VCC = VCCO = GND)
Symbol
Characteristic
-40°C
0°C
Min Typ Max Min Typ Max Min
VOH Output HIGH Voltage1 -1080
VOL Output LOW Voltage1 -1950
-890 -1020
-1650 -1950
-840 -980
-1630 -1950
VIH
Input HIGH Voltage
-1230
-890 -1170
-840 -1130
VIL
Input LOW Voltage
-1950
-1500 -1950
-1480 -1950
IIH Input HIGH Current
150 150
IIL
Input LOW Current
0.5
0.5
0.5
IEE Power Supply Current
120 145
120 145
1. Each output is terminated through a 50Ω resistor to VCC – 2V.
25°C
Typ
120
Max
-810
-1630
-810
-1480
150
145
Min
-910
-1950
-1060
-1950
0.5
85°C
Typ
120
Max
-720
-1595
-720
-1445
150
145
Unit
mV
mV
mV
mV
μA
μA
mA
November 2006 * REV - 3
www.azmicrotek.com
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