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IW4015B 반도체 회로 부품 판매점

Dual 4-Bit Static Shift Register



IK Semiconductor 로고
IK Semiconductor
IW4015B 데이터시트, 핀배열, 회로
TECHNICAL DATA
Dual 4-Stage Static Shift Register
IW4015B
The IW4015B consists of two identical, independent, 4-stage serial-
input/parallel-output registers. Each register has independent CLOCK and
RESET inputs as well as a single serial DATA input. “Q” outputs are
available from each of the four stages on both registers. All register stages
are D-type, master-slave flip-flops. The logic level present at the DATA
input is transferred into the first register stage and shifted over one stage
at each positive-going clock transition. Resetting of all stages is
accomplished by a high level on the reset line. Register expansion to 8
stages using one IW4015B package, or to more than 8 stages using
additional IW4015B’s is possible.
Operating Voltage Range: 3.0 to 18 V
Maximum input current of 1 µA at 18 V over full package-temperature
range; 100 nA at 18 V and 25°C
Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
ORDERING INFORMATION
IW4015BN Plastic
IW4015BD SOIC
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
www.datasheet4u.cPPoIINNm81=6=GVNCDC
FUNCTION TABLE
Inputs
Clock Data Reset
LL
HL
XL
X XH
Outputs
Q1 Qn
L Qn-1
H Qn-1
No change
LL
X = don’t care
1


IW4015B 데이터시트, 핀배열, 회로
IW4015B
MAXIMUM RATINGS*
Symbol
VCC
VIN
VOUT
IIN
PD
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
Value
-0.5 to 20
-0.5 to VCC 0.5
-0.5 to VCC 0.5
±10
750
500
PD Power Dissipation per Output Transistor
Tstg Storage Temperature
100
-65 to 150
TL Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
Unit
V
V
V
mA
mW
mW
°C
°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC
VIN, VOUT
TA
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Min Max Unit
3.0 18
V
0 VCC V
-55 125
°C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or
VOUT)VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused
outputs must be left open.
2




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Dual 4-Bit Static Shift Register - IK Semiconductor