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SY100E167 반도체 회로 부품 판매점

6-BIT 2:1 MUX-REGISTER



Micrel Semiconductor 로고
Micrel Semiconductor
SY100E167 데이터시트, 핀배열, 회로
SY NERGY
SEMICONDUCTOR
6-BIT 2:1 MUX-REGISTER
SY10E167
SY1S0YE10106E7167
SY100E167
FEATURES
s 1000MHz min. operating frequency
s Extended 100E VEE range of –4.2V to –5.5V
s 800ps max. clock to output
s Single-ended outputs
s Asynchronous Master Reset
s Dual clocks
s Fully compatible with industry standard 10KH,
100K ECL levels
s Internal 75Kinput pulldown resistors
s ESD protection of 2000V
s Fully compatible with Motorola MC10E/100E167
s Available in 28-pin PLCC package
BLOCK DIAGRAM
DESCRIPTION
The SY10/100E167 offer six 2:1 multiplexers followed
by D flip-flops with single-ended outputs, designed for use
in new, high-performance ECL systems. The Select (SEL)
control allows one of the two data inputs to the multiplexer
to pass through. The two external clock signals (CLK1,
CLK2) are gated through a logical OR operation before use
as control for the six flip-flops. The selected data are
transferred to the flip-flops on the rising edge of CLK1 or
CLK2 (or both).
The multiplexer operation is controlled by the Select
(SEL) signal which selects one of the two bits of input data
at each mux to be passed through.
When a logic HIGH is applied to the Master Reset (MR)
signal, it operates asychronously to take all outputs Q to a
logic LOW.
PIN CONFIGURATION
D0a
D0b
D1a
D1b
D2a
D2b
D3a
D3b
D4a
D4b
D5a
D5b
SEL
CLK1
CLK2
MR
MUX
SEL
MUX
SEL
MUX
SEL
MUX
SEL
MUX
SEL
MUX
SEL
© 1999 Micrel-Synergy
DQ
R
DQ
R
DQ
R
DQ
R
DQ
R
DQ
R
Q0
Q1
Q2
Q3
Q4
Q5
D5b
CLK1
CLK2
VEE
MR
SEL
D0a
25 24 23 22 21 20 19
26 18
27 17
28 16
TOP VIEW
1 PLCC 15
2
J28-1
14
3 13
4 12
5 6 7 8 9 10 11
Q5
Q4
VCC
Q3
Q2
VCCO
Q1
PIN NAMES
Pin
D0a–D5a
D0b–D5b
SEL
CLK1, CLK2
MR
Q0–Q5
VCCO
5-127
Function
Input Data a
Input Data b
Select Input
Clock Inputs
Master Reset
Data Outputs
VCC to Output
Rev.: C Amendment: /1
Issue Date: February, 1998


SY100E167 데이터시트, 핀배열, 회로
SY NERGY
SEMICONDUCTOR
TRUTH TABLE
SEL
H
L
Data
a
b
SY10E167
SY100E167
DC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = 0°C
TA = +25°C
TA = +85°C
Symbol
Parameter
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
IIH Input HIGH Current
— — 150 — — 150 — — 150
IEE Power Supply Current
10E — 94 113 — 94 113 — 94 113
100E — 94 113 — 94 113 — 108 130
Unit
µA
mA
Condition
AC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = 0°C
TA = +25°C
TA = +85°C
Symbol
Parameter
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
fMAX Max. Toggle Frequency
1000 1400 — 1000 1400 — 1000 1400 — MHz
tPLH Propagation Delay to Output
ps
tPHL
CLK
450 650 800 450 650 800 450 650 800
MR 450 650 850 450 650 850 450 650 850
tS Set-up Time
D
SEL
100 –50 — 100 –50
275 125 — 275 125
— 100 –50
— 275 125
ps
tH Hold Time
D
SEL
300 50 — 300 50 — 300 50 —
75 –125 — 75 –125 — 75 –125 —
ps
tRR Reset Recovery Time
750 550 — 750 550 — 750 550 — ps
tPW Minimum Pulse Width
CLK, MR
400 — — 400 — — 400 — — ps
tskew Within-Device Skew
— 75 — — 75 — — 75 — ps
tr Rise/Fall Time
tf 20% to 80%
300 450 800 300 450 800 300 450
NOTE:
1. Within-device skew is defined as identical transitions on similar paths through a device.
800
ps
PRODUCT ORDERING CODE
Ordering
Code
SY10E167JC
SY10E167JCTR
SY100E167JC
SY100E167JCTR
Package
Type
J28-1
J28-1
J28-1
J28-1
Operating
Range
Commercial
Commercial
Commercial
Commercial
5-128
Condition
1




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SY100E167 register

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