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74HC7731 반도체 회로 부품 판매점

Quad 64-bit static shift register



Philips 로고
Philips
74HC7731 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT7731
Quad 64-bit static shift register
Product specification
File under Integrated Circuits, IC06
September 1993


74HC7731 데이터시트, 핀배열, 회로
Philips Semiconductors
Quad 64-bit static shift register
Product specification
74HC/HCT7731
FEATURES
Frequency range DC to 100 MHz.
Separate serial data inputs
Cascadable
Functionally compatible with
HEF 4731
Includes recycling mode
Direct shift out
Output capability: Standard
ICC category: LSI.
APPLICATIONS
Data storage
Delay line.
GENERAL DESCRIPTION
The HC/HCT7731 are high-speed
Si-gate CMOS devices. They are
specified in compliance with JEDEC
standard no. 7A.
The HC/HCT7731 are quad 64-bit
static shift registers with a recycling
mode. Each register has separate
data inputs Da to Dd, clock inputs CPa
to CPd and data outputs Qa to Qd.
Data shifts one place towards the
output, each LOW to HIGH transition
of the clock pulse. Each recycling
mode input controls two registers
RECab for registers A and B and
RECcd for registers C and D. When
the REC input is HIGH, the device is
in the recycling mode and data at the
output is shifted back into the input of
the register, so after 64 clock pulses
the contents of a register is again in
its original position. This enables the
user to tap off data from any position.
When the REC input is LOW external
data can be shifted in.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns.
SYMBOL
PARAMETER
TYP.
CONDITIONS
UNIT
HC HCT
tPHL/tPLH
fmax
CI
CPD
propagation delay
CPa-d to Qa-d
maximum clock
frequency
input capacitance
power dissipation
capacitance per register
CL = 15 pF;
VCC = 5 V
notes 1, 2
and 3
15 20 ns
100 100 MHz
3.5 3.5
58 61
pF
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = (CPD x VCC2 x fi) + (CL + VCC2 x fo) + (Ipull-up x VCC)
where:
fi = input frequency in MHz.
fo = output frequency in MHz.
VCC = supply voltage in V.
CL = output load capacitance in pF.
Ipull-up = pull-up currents in µA.
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC 1.5 V.
3. See also power dissipation information.
ORDERING INFORMATION
EXTENDED TYPE
NUMBER
74HC/HCT7731N
74HC/HCT7731D
PINS
16
16
PACKAGE
PIN POSITION MATERIAL
DIL
SO16
plastic
plastic
CODE
SOT38Z
SOT109A
September 1993
2




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74HC7731 register

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74HC7731

Quad 64-bit static shift register - Philips