파트넘버.co.kr 74HC164 데이터시트 PDF


74HC164 반도체 회로 부품 판매점

8 BIT SIPO SHIFT REGISTER



STMicroelectronics 로고
STMicroelectronics
74HC164 데이터시트, 핀배열, 회로
. HIGH SPEED
tPD = 15 ns (TYP.) AT VCC = 5 V
. LOW POWER DISSIPATION
ICC = 4 µA (MAX.) AT TA = 25 °C
. OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
. BALANCED PROPAGATION DELAYS
tPLH = tPHL
. SYMMETRICAL OUTPUT IMPEDANCE
IOL = IOH= 4 mA (MIN.)
. HIGH NOISE IMMUNITY
VNIH = VNIL = 28 % VCC (MIN.)
. WIDE OPERATING VOLTAGE RANGE
VCC (OPR) = 2 V TO 6 V
. PIN AND FUNCTION COMPATIBLE
WITH 54/74LS164
M54HC164
M74HC164
8 BIT SIPO SHIFT REGISTER
B1R
(Plastic Package)
F1R
(Ceramic Package)
M 1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M 54HC 16 4F 1R
M 74H C1 64 M1 R
M 74HC 16 4B 1R
M 74H C1 64 C1 R
PIN CONNECTIONS (top view)
DESCRIPTION
The M54/74HC164 is a high speed CMOS 8 BIT
SIPO SHIFT REGISTER fabricated in silicon gate
C2MOS technology. It has the same high speed per-
formance of LSTTL combined with true CMOS low
power consumption.
The HC164 is an 8 bit shift register with serial data
entry and an output from each of the eight stages.
Data is entered serially through one of two inputs (A
or B), either of these inputs can be used as an active
high enable for data entry through the other input.
An unused input must be high, or both inputs con-
nected together. Each low-to-high transition on the
clock input shifts data one place to the right and
enters into QA, the logic NAND of the two data inputs
(A B), the data that existed before the rising clock
edge. A low level on the clear input overrides all
other inputs and clears the register asynchronously,
forcing all Q outputs low.
All inputs are equipped with protection circuits
against static discharge and transient excess volt-
age.
October 1992
NC =
No Internal
Connection
1/12


74HC164 데이터시트, 핀배열, 회로
M54/M74HC164
INPUT AND OUTPUT EQUIVALENT CIRCUIT
TRUTH TABLE
INPUTS
CLEAR
CLOCK
SERIAL IN
AB
QA
LXXXL
H XX
H L XL
H XL L
H HHH
X: Don’t Care
QAn - QGn : The level of QA -QG, respectively. before the most-recent transition of th clock.
OUTPUS
QB ............
L ............
NO CHANGE
QAn
............
QAn
............
QAn
............
LOGIC DIAGRAM
QH
L
QGn
QGn
QGn
2/12




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74HC164 register

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