74F794SC 반도체 회로 부품 판매점
8-Bit Register with Readback
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 Fairchild |
March 1990
Revised August 1999
74F794
8-Bit Register with Readback
General Description
The 74F794 is an 8-bit register with readback capability
designed to store data as well as read the register informa-
tion back onto the data bus. The I/O bus (D bus) has 3-
STATE outputs. Current sinking capability is 64 mA on both
the D and Q busses.
Data is loaded into the registers on the LOW-to-HIGH tran-
sition of the clock (CP). The output enable (OE) is used to
enable data on D0–D7. When OE is LOW, the output of the
registers is enabled on D0–D7, enabling D as an output
bus. When OE is HIGH, D0–D7 are inputs to the registers
configuring D as an input bus.
Features
s 3-STATE outputs on the I/O port
s D and Q output sink capability of 64 mA
s Functionally and pin equivalent to the 74LS794
Ordering Code:
Order Number Package Number
Package Description
74F794SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F794PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
© 1999 Fairchild Semiconductor Corporation DS010652
www.fairchildsemi.com
Input Loading/Fan-Out
Pin Names
OE
CP
D0–D7
Q0–Q7
Description
Output Enable Input
Clock Pulse Inputs
D Bus Inputs/
3-STATE Outputs
Q Bus Outputs
HIGH/LOW
(U.L.)
Current
1.0/1.0 20 µA/−0.6 mA
1.0/1.0
20 µA/−0.6 mA
3.5/1.083 70 µA/−650 µA
750/106.6 −15 mA/64 mA
750/106.6 −15 mA/64 mA
Truth Table
Logic Diagram
Inputs
Outputs
CP OE Q
D
L or H or ↓
L or H or ↓
↑
↑
L Qn
H Qn
L Qn
HD
Output, Q
Input
Output, Q (Note 1)
Input
Note 1: In this case the output of the register is clocked to the inputs and
the overall Q output is unchanged at Qn.
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74F794SC register
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