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National |
December 1994
54F 74F676
16-Bit Serial Parallel-In Serial-Out Shift Register
General Description
The ’F676 contains 16 flip-flops with provision for synchro-
nous parallel or serial entry and serial output When the
Mode (M) input is HIGH information present on the parallel
data (P0 – P15) inputs is entered on the falling edge of the
Clock Pulse (CP) input signal When M is LOW data is shift-
ed out of the most significant bit position while information
present on the Serial (SI) input shifts into the least signifi-
cant bit position A HIGH signal on the Chip Select (CS)
input prevents both parallel and serial operations
Features
Y 16-bit parallel-to-serial conversion
Y 16-bit serial-in serial-out
Y Chip select control
Y Slim 24 lead 300 mil package
Commercial
74F676PC
74F676SPC
74F676SC (Note 1)
Military
54F676DM (Note 2)
54F676SDM (Note 2)
54F676FM (Note 2)
54F676LM (Note 2)
Package
Number
N24A
N24C
J24A
J24F
M24B
W24C
E28A
Package Description
24-Lead (0 600 Wide) Molded Dual-In-Line
24-Lead (0 300 Wide) Molded Dual-In-Line
24-Lead (0 600 Wide) Ceramic Dual-In-Line
24-Lead (0 300 Wide) Ceramic Dual-In-Line
24-Lead (0 300 Wide) Molded Small Outline JEDEC
24-Lead Cerpack
24-Lead Ceramic Leadless Chip Carrier Type C
Note 1 Devices also available in 13 reel Use suffix e SCX
Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB
Connection Diagrams
Pin Assignment
for DIP SOIC and Flatpak
Pin Assignment
for LCC
TL F 9588 – 2
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 9588
TL F 9588 – 3
RRD-B30M105 Printed in U S A
Logic Symbols
IEEE IEC
TL F 9588 – 1
Unit Loading Fan Out
Pin Names
P0 – P15
CS
CP
M
SI
SO
Description
Parallel Data Inputs
Chip Select Input (Active LOW)
Clock Pulse Input (Active LOW)
Mode Select Input
Serial Data Input
Serial Output
54F 74F
UL
HIGH LOW
10 10
10 10
10 10
10 10
10 10
50 33 3
Input IIH IIL
Output IOH IOL
20 mA b0 6 mA
20 mA b0 6 mA
20 mA b0 6 mA
20 mA b0 6 mA
20 mA b0 6 mA
b1 mA 20 mA
TL F 9588 – 4
Functional Description
The 16-bit shift register operates in one of three modes as
indicated in the Shift Register Operations Table
HOLD a HIGH signal on the Chip Select (CS) input pre-
vents clocking and data is stored in the sixteen registers
Shift Serial Load data present on the SI pin shifts into
the register on the falling edge of CP Data enters the Q0
position and shifts toward Q15 on successive clocks finally
appearing on the SO pin
Parallel Load data present on P0 – P15 are entered into
the register on the falling edge of CP The SO output repre-
sents the Q15 register output
To prevent false clocking CP must be LOW during a LOW-
to-HIGH transition of CS
Block Diagram
Shift Register Operations Table
Control Input
CS M
CP
HX
X
L LK
L HK
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
K e HIGH-to-LOW Transition
Operating Mode
Hold
Shift Serial Load
Parallel Load
TL F 9588 – 5
2
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