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PDF 74F673ASC Data sheet ( Hoja de datos )
| Número de pieza | 74F673ASC | |
| Descripción | 16-Bit Serial-In / Serial/Parallel-Out Shift Register | |
| Fabricantes | Fairchild | |
| Logotipo |  |
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April 1988
Revised August 1999
74F673A
16-Bit Serial-In, Serial/Parallel-Out Shift Register
General Description
The 74F673A contains a 16-bit serial-in, serial-out shift
register and a 16-bit Parallel-Out storage register. A single
pin serves either as an input for serial entry or as a 3-
STATE serial output. In the Serial-Out mode, the data recir-
culates in the shift register. By means of a separate clock,
the contents of the shift register are transferred to the stor-
age register for parallel outputting. The contents of the stor-
age register can also be parallel loaded back into the shift
register. A HIGH signal on the Chip Select input prevents
both shifting and parallel transfer. The storage register may
be cleared via STMR.
Features
s Serial-to-parallel converter
s 16-bit serial I/O shift register
s 16-bit parallel-out storage register
s Recirculating serial shifting
s Recirculating parallel transfer
s Common serial data I/O pin
s Slim 24 lead package
Ordering Code:
Order Number Package Number
Package Description
74F673ASC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F673APC
N24A
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600 Wide
74F673ASPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
© 1999 Fairchild Semiconductor Corporation DS009585
www.fairchildsemi.com
1 page  
AC Electrical Characteristics
Symbol
Parameter
fMAX
tPLH
tPHL
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
Maximum Clock Frequency
Propagation Delay
STCP to Qn
Propagation Delay
STMR to Qn
Propagation Delay
SHCP to SI/O
Output Enable Time
CS to SI/O
Output Disable Time
CS to SI/O
Output Enable Time
R/W to SI/O
Output Disable Time
R/W to SI/O
AC Operating Requirements
Symbol
Parameter
tS(H)
tS(L)
tH(H)
tH(L)
tS(H)
tS(L)
tH(H)
tH(L)
Setup Time, HIGH or LOW
CS or R/W to STCP
Hold Time, HIGH or LOW
CS or R/W to STCP
Setup Time, HIGH or LOW
SI/O to SHCP
Hold Time, HIGH or LOW
SI/O to SHCP
TA = +25°C
VCC = +5.0V
CL = 50 pF
Min Typ Max
100 130
3.0 8.0 10.5
3.0
10.5
13.5
6.0
16.5
20.5
4.0 6.5 8.5
4.5 8.0 10.5
5.0 8.5 11.0
5.5 9.0 11.5
3.5 5.5 7.5
3.0 4.5 6.5
4.5 7.5 9.5
4.5 8.0 10.0
3.0 5.5 7.0
2.5 4.0 5.5
TA = 0°C to +70°C
VCC = +5.0V
CL = 50 pF
Min Max
85
2.5 12.0
2.5 15.0
5.5 22.5
3.5 9.5
4.0 12.0
4.0 12.5
4.5 13.0
3.0 8.5
2.5 7.5
4.0 10.5
4.0 11.5
2.5 8.0
2.0 6.5
Units
MHz
ns
ns
ns
ns
ns
TA = +25°C
VCC = +5.0V
Min Max
3.5
6.0
0
0
3.0
3.0
3.0
3.0
TA = 0°C to +70°C
VCC = +5.0V
Min Max
4.0
7.0
0
0
3.5
3.5
3.5
3.5
Units
ns
ns
5 www.fairchildsemi.com
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet 74F673ASC.PDF ] | |
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