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National |
May 1995
54F 74F398 54F 74F399
Quad 2-Port Register
General Description
The ’F398 and ’F399 are the logical equivalents of a quad
2-input multiplexer feeding into four edge-triggered flip-
flops A common Select input determines which of the two
4-bit words is accepted The selected data enters the flip-
flops on the rising edge of the clock The ’F399 is the 16-pin
version of the ’F398 with only the Q outputs of the flip-flops
available
Features
Y Select inputs from two data sources
Y Fully positive edge-triggered operation
Y Both true and complement outputs ’F398
Y Guaranteed 4000V minimum ESD protection
’F399
Commercial
74F398PC
74F398SC (Note 1)
74F399PC
74F399SC (Note 1)
74F399SJ (Note 1)
Military
54F398DM (Note 2)
54F398FM (Note 2)
54F398LM (Note 2)
54F399DM (Note 2)
54F399FM (Note 2)
54F399LM (Note 2)
Package
Number
N20A
J20A
M20B
W20A
E20A
N20A
J20A
M20B
M20D
W20A
E20A
Package Description
20-Lead (0 300 Wide) Molded Dual-In-Line
20-Lead Ceramic Dual-In-Line
20-Lead (0 300 Wide) Molded Small Outline JEDEC
20-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier Type C
20-Lead (0 300 Wide) Molded Dual-In-Line
20-Lead Ceramic Dual-In-Line
20-Lead (0 300 Wide) Molded Small Outline JEDEC
20-Lead (0 300 Wide) Molded Small Outline EIAJ
20-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier Type C
Note 1 Devices also available in 13 reel Use suffix e SCX and SJX
Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB
Connection Diagrams
Pin Assignment
for LCC
’F398
Pin Assignment
for DIP SOIC and Flatpak
TL F 9533 – 5
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 9533
TL F 9533 – 6
RRD-B30M75 Printed in U S A
Connection Diagrams (Continued)
’F399
Logic Symbols
’F398
TL F 9533–7
IEEE IEC
’F398
TL F 9533 – 8
’F399
TL F 9533–2
TL F 9533–4
’F399
TL F 9533 – 1
Unit Loading Fan Out
Pin Names
Description
S
CP
I0a – I0d
I1a – I1d
Qa – Qd
Qa – Qd
Common Select Input
Clock Pulse Input (Active Rising Edge)
Data Inputs from Source 0
Data Inputs from Source 1
Register True Outputs
Register Complementary Outputs (’F398)
54F 74F
UL
HIGH LOW
10 10
10 10
10 10
10 10
50 33 3
50 33 3
Input IIH IIL
Output IOH IOL
20 mA b0 6 mA
20 mA b0 6 mA
20 mA b0 6 mA
20 mA b0 6 mA
b1 mA 20 mA
b1 mA 20 mA
2
TL F 9533 – 3
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