PDF 74F322PC Data sheet ( Hoja de datos )

Número de pieza	74F322PC
Descripción	Octal Serial/Parallel Register with Sign Extend
Fabricantes	Fairchild
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No Preview Available ! April 1988 Revised April 1999 74F322 Octal Serial/Parallel Register with Sign Extend General Description The 74F322 is an 8-bit shift register with provision for either serial or parallel loading and with 3-STATE parallel outputs plus a bi-state serial output. Parallel data inputs and paral- lel outputs are multiplexed to minimize pin count. State changes are initiated by the rising edge of the clock. Four synchronous modes of operation are possible: hold (store), shift right with serial entry, shift right with sign extend and parallel load. An asynchronous Master Reset (MR) input overrides clocked operation and clears the register. Features s Multiplexed parallel I/O ports s Separate serial input and output s Sign extend function s 3-STATE outputs for bus applications Ordering Code: Order Number Package Number Package Description 74F322PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 1999 Fairchild Semiconductor Corporation DS009516.prf www.fairchildsemi.com 1 page AC Electrical Characteristics Symbol Parameter fMAX tPLH tPHL tPLH tPHL tPHL tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ Maximum Clock Frequency Propagation Delay CP to I/On Propagation Delay CP to Q0 Propagation Delay MR to I/On Propagation Delay MR to Q0 Output Enable Time OE to I/On Output Disable Time OE to I/On Output Enable Time S/P to I/On Output Disable Time S/P to I/On TA = +25°C VCC = +5.0V CL = 50 pF Min Typ Max 70 90 3.5 7.0 7.5 5.0 8.5 11.0 3.5 7.0 9.0 3.5 7.0 8.0 6.0 10.0 13.0 5.5 7.5 12.0 3.0 6.5 9.0 4.0 8.5 11.0 2.0 4.5 6.0 2.0 5.0 7.0 4.5 8.0 10.5 5.5 10.0 14.0 5.0 9.0 11.5 6.0 12.0 15.5 AC Operating Requirements TA = −55°C to +125°C CL = 50 pF TA = 0°C to +75°C CL = 50 pF Min Max Min Max 50 70 3.5 9.5 3.5 8.5 3.5 10.0 5.0 12.0 3.5 11.0 3.5 10.0 3.5 10.0 3.5 9.0 6.0 15.0 6.0 14.0 5.5 14.0 5.5 13.0 3.0 12.5 3.0 10.0 4.0 14.5 4.0 12.0 2.0 8.0 2.0 7.0 2.0 10.0 2.0 8.0 4.5 13.5 4.5 11.5 5.5 17.0 5.5 15.0 5.0 16.5 5.0 12.5 6.0 19.5 6.0 16.5 Symbol Parameter tS(H) tS(L) tH(H) tH(L) tS(H) tS(L) tH(H) tH(L) tSH) tS(L) tH(H) tH(L) tS(H) tS(L) tS(H) tS(L) tH(H) tH(L) tW(H) tW(L) tW(L) tREC Setup Time, HIGH or LOW RE to CP Hold Time, HIGH or LOW RE to CP Setup Time, HIGH or LOW D0, D1 or I/On to CP Hold Time, HIGH or LOW D0, D1 or I/On to CP Setup Time, HIGH or LOW SE to CP Hold Time, HIGH or LOW SE to CP Setup Time, HIGH or LOW S/P to CP Setup Time, HIGH or LOW S to CP Hold Time, HIGH or LOW S or S/P to CP CP Pulse Width, HIGH or LOW MR Pulse Width, LOW Recovery Time MR to CP TA = +25°C VCC = +5.0V Min Max 6.0 14.0 0 0 6.5 6.5 2.0 2.0 7.0 2.5 2.0 0.0 11.0 13.5 6.5 9.0 0 0 7.0 TA = −55°C to +125°C TA = 0C to +75°C Min Max Min Max 14.0 18.0 7.0 16.0 00 00 8.5 7.5 8.5 7.5 3.0 3.0 3.0 3.0 9.0 8.0 11.0 3.5 2.0 2.0 1.0 0.0 13.0 21.0 12.0 15.5 8.5 7.5 11.0 10.0 1.0 0 00 8.0 7.0 5.5 7.5 6.5 8.0 12.0 8.0 Units MHz ns ns ns ns ns Units ns ns ns ns ns ns ns ns ns ns ns 5 www.fairchildsemi.com 5 Page

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