74F299 반도체 회로 부품 판매점

Octal Universal Shift/Storage Register with Common Parallel I/O Pins



Fairchild 로고
Fairchild
74F299 데이터시트, 핀배열, 회로
April 1988
Revised August 1999
74F299
Octal Universal Shift/Storage Register
with Common Parallel I/O Pins
General Description
The 74F299 is an 8-bit universal shift/storage register with
3-STATE outputs. Four modes of operation are possible:
hold (store), shift left, shift right and load data. The parallel
load inputs and flip-flop outputs are multiplexed to reduce
the total number of package pins. Additional outputs, Q0
Q7, are provided to allow easy serial cascading. A separate
active LOW Master Reset is used to reset the register.
Features
s Common parallel I/O for reduced pin count
s Additional serial inputs and outputs for expansion
s Four operating modes: shift left, shift right, load and
store
s 3-STATE outputs for bus-oriented applications
s Guaranteed 4000V minimum ESD protection
Ordering Code:
Order Number Package Number
Package Description
74F299SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F299SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F299PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation DS009515
www.fairchildsemi.com

74F299 데이터시트, 핀배열, 회로
Unit Loading/Fan Out
Pin Names
Description
CP
DS0
DS7
S0, S1
MR
OE1, OE2
I/O0–I/O7
Q0, Q7
Clock Pulse Input (Active Rising Edge)
Serial Data Input for Right Shift
Serial Data Input for Left Shift
Mode Select Inputs
Asynchronous Master Reset Input (Active LOW)
3-STATE Output Enable Inputs (Active LOW)
Parallel Data Inputs or
3-STATE Parallel Outputs
Serial Outputs
U.L.
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
1.0/2.0
1.0/1.0
1.0/1.0
3.5/1.083
150/40(33.3)
50/33.3
Functional Description
The 74F299 contains eight edge-triggered D-type flip-flops
and the interstage logic necessary to perform synchronous
shift left, shift right, parallel load and hold operations. The
type of operation is determined by S0 and S1, as shown in
the Mode Select Table. All flip-flop outputs are brought out
through 3-STATE buffers to separate I/O pins that also
serve as data inputs in the parallel load mode. Q0 and Q7
are also brought out on other pins for expansion in serial
shifting of longer words.
A LOW signal on MR overrides the Select and CP inputs
and resets the flip-flops. All other state changes are initi-
ated by the rising edge of the clock. Inputs can change
when the clock is in either state provided only that the rec-
ommended setup and hold times, relative to the rising edge
of CP, are observed.
A HIGH signal on either OE1 or OE2 disables the 3-STATE
buffers and puts the I/O pins in the high impedance state.
In this condition the shift, hold, load and reset operations
can still occur. The 3-STATE outputs are also disabled by
HIGH signals on both S0 and S1 in preparation for a paral-
lel load operation.
Logic Diagram
Mode Select Table
Inputs
Response
MR S1 S0 CP
L X X X Asynchronous Reset; Q0–Q7 = LOW
H H H
Parallel Load; I/On Qn
H L H
Shift Right; DS0 Q0, Q0 Q1, etc.
H H L
Shift Left; DS7 Q7, Q7 Q6, etc.
H L L X Hold
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
Input IIH/IIL
Output IOH/IOL
20 µA/0.6 mA
20 µA/0.6 mA
20 µA/0.6 mA
20 µA/1.2 mA
20 µA/0.6 mA
20 µA/0.6 mA
70 µA/0.65 mA
3 mA/24 mA (20 mA)
1 mA/20 mA
www.fairchildsemi.com
Please note that this diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
2




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74F299 register

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