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PDF 74F199 Data sheet ( Hoja de datos )
| Número de pieza | 74F199 | |
| Descripción | 8-bit parallel-access shift register | |
| Fabricantes | Philips | |
| Logotipo |  |
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Philips Semiconductors FAST Products
8-bit parallel-access shift register
Product specification
74F199
FEATURES
• Buffered clock and control inputs
• Shift right and parallel load capability
• Fully synchronous data transfers
• J-K(D) inputs to first stage
• Clock enable for hold (do nothing) mode
• Asynchronous Master Reset
DESCRIPTION
The 74F199 is an 8-bit Parallel Access Shift Register and its
functional characteristics are indicated in the Logic Diagram and
Function Table. The device is useful in a variety of shifting, counting
and storage applications. It performs serial, parallel, serial-to-parallel,
or parallel–to-serial data transfers at very high speeds.
The 74F199 operates in two primary modes: shift right (Q0→Q1)
and parallel load, which are controlled by the state of the Parallel
Enable (PE) input. Serial data enters the first flip-flop (Q0) via the J
and K inputs when the PE input is High, and is shifted one bit in the
direction Q0→Q1→Q2 following each Low-to-High clock transition.
The J and K inputs provide the flexibility of the J-K type input for
special applications, and by tying the two together the simple D-type
input is made for general applications.
The device appears as eight common clocked D flip-flops when the
PE input is Low. After the Low-to-High clock transition, data on the
parallel inputs (D0–D7) is transferred to the respective Q0–Q7
outputs.
All parallel and serial data transfers are synchronous, occurring after
each Low-to-High clock transition. The 74F199 utilizes
edge-triggered, therefore there is no restriction on the activity of the
J, K, Dn, and PE inputs for logic operation, other than the setup and
hold time requirements.
A Low on the Master Reset (MR) input overrides all other inputs and
clears the register asynchronously forcing all bit positions to a Low
state.
PIN CONFIGURATION
K1
J2
D0 3
Q0 4
D1 5
Q1 6
D2 7
Q2 8
D3 9
Q3 10
CE 11
GND 12
24 VCC
23 PE
22 D7
21 Q7
20 D6
19 Q6
18 D5
17 Q5
16 D4
15 Q4
14 MR
13 CP
SF00152
TYPE
74F199
TYPICAL fMAX
95MHz
TYPICAL
SUPPLY CURRENT
(TOTAL)
70mA
ORDERING INFORMATION
DESCRIPTION
24-pin plastic slim DIP
(300mil)
COMMERCIAL RANGE
VCC = 5V ±10%, Tamb = 0°C to +70°C
N74F199N
24-pin plastic SOL
N74F199D
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F (U.L.) HIGH/LOW
D0–D7
Parallel data inputs
1.0/1.0
J, K J and K inputs
1.0/1.0
PE Parallel Enable input
1.0/1.0
CE Clock Enable input
1.0/1.0
DP Clock Pulse inputs (Active rising edge)
1.0/1.0
MR Master Reset input (Active Low)
1.0/1.0
Q0–Q7
Data outputs
50/33
NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
LOAD VALUE HIGH/LOW
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
1.0mA/20mA
June 15, 1988
1 853–0082 93568
1 page  
Philips Semiconductors FAST Products
8-bit parallel-access shift register
Product specification
74F199
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST CONDITIONS1
LIMITS
MIN TYP2 MAX
UNIT
VOH High-level output voltage
VCC = MIN, VIL = MAX ±10%VCC
VIH = MIN, IOH = MAX ±5%VCC
2.5
2.7
3.4
V
VOL Low-level output voltage
VCC = MIN, VIL = MAX ±10%VCC
VIH = MIN, IOL = MAX ±5%VCC
0.35 0.50
0.35 0.50
V
VIK Input clamp voltage
VCC = MIN, II = IIK
–0.73 –1.2
V
II
Input current at maximum input voltage
VCC = MAX, VI = 7.0V
100 µA
IIH High-level input current
VCC = MAX, VI = 2.7V
20 µA
IIL Low-level input current
VCC = MAX, VI = 0.5V
–0.6 mA
IOS Short-circuit output current3
VCC = MAX
–60
–150
mA
ICC Supply current (total)
ICCH
ICCL
VCC = MAX
65 90
75 105
mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at VCC = 5V, Tamb = 25°C.
3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, IOS tests should be performed last.
June 15, 1988
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet 74F199.PDF ] | |
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