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74F194PC 반도체 회로 부품 판매점

4-Bit Bidirectional Universal Shift Register



Fairchild 로고
Fairchild
74F194PC 데이터시트, 핀배열, 회로
April 1988
Revised March 2000
74F194
4-Bit Bidirectional Universal Shift Register
General Description
The 74F194 is a high-speed 4-bit bidirectional universal
shift register. As a high-speed, multifunctional, sequential
building block, it is useful in a wide variety of applications. It
may be used in serial-serial, shift left, shift right, serial-par-
allel, parallel-serial, and parallel-parallel data register
transfers.
Features
s Typical shift frequency of 150 MHz
s Asynchronous master reset
s Hold (do nothing) mode
s Fully synchronous serial or parallel data transfers
Ordering Code:
Order Number Package Number
Package Description
74F194SC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74F194SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F194PC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 2000 Fairchild Semiconductor Corporation DS009498
www.fairchildsemi.com


74F194PC 데이터시트, 핀배열, 회로
Unit Loading/Fan Out
Pin Names
Description
S0, S1
P0–P3
DSR
DSL
CP
MR
Q0–Q3
Mode Control Inputs
Parallel Data Inputs
Serial Data Input (Shift Right)
Serial Data Input (Shift Left)
Clock Pulse Input (Active Rising Edge)
Asynchronous Master Reset Input (Active LOW)
Parallel Outputs
U.L.
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
50/33.3
Input IIH/IIL
Output IOH/IOL
20 µA/0.6 mA
20 µA/0.6 mA
20 µA/0.6 mA
20 µA/0.6 mA
20 µA/0.6 mA
20 µA/0.6 mA
1 mA/20 mA
Functional Description
The 74F194 contains four edge-triggered D-type flip-flops
and the necessary interstage logic to synchronously per-
form shift right, shift left, parallel load and hold operations.
Signals applied to the Select (S0, S1) inputs determine the
type of operation, as shown in the Mode Select Table. Sig-
nals on the Select, Parallel data (P0–P3) and Serial data
(DSR, DSL) inputs can change when the clock is in either
state, provided only that the recommended setup and hold
times, with respect to the clock rising edge, are observed.
A LOW signal on Master Reset (MR) overrides all other
inputs and forces the outputs LOW.
Mode Select Table
Operating
Inputs
Outputs
Mode
MR S1 S0 DSR DSL Pn Q0 Q1 Q2 Q3
Reset
L XX X X XLLLL
Hold
H l l X X X q0 q1 q2 q3
Shift Left
H h l X l X q1 q2 q3 L
H h l X h X q1 q2 q3 H
Shift Right H l h l X X L q0 q1 q2
H l h h X X H q0 q1 q2
Parallel Load H h h X X pn p0 p1 p2 p3
H (h) = HIGH Voltage Level
L (l) = LOW Voltage Level
pn (qn) = Lower case letters indicate the state of the referenced input (or
output) one setup time prior to the LOW-to-HIGH clock transition.
X = Immaterial
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com
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