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74VHC164 반도체 회로 부품 판매점

8-Bit Serial-In/ Parallel-Out Shift Register



Fairchild Semiconductor 로고
Fairchild Semiconductor
74VHC164 데이터시트, 핀배열, 회로
August 1993
Revised April 1999
74VHC164
8-Bit Serial-In, Parallel-Out Shift Register
General Description
The VHC164 is an advanced high-speed CMOS device
fabricated with silicon gate CMOS technology. It achieves
the high-speed operation similar to equivalent Bipolar
Schottky TTL while maintaining the CMOS low power dissi-
pation. The VHC164 is a high-speed 8-Bit Serial-In/Paral-
lel-Out Shift Register. Serial data is entered through a 2-
input AND gate synchronous with the LOW-to-HIGH transi-
tion of the clock. The device features an asynchronous
Master Reset which clears the register, setting all outputs
LOW independent of the clock. An input protection circuit
insures that 0V to 7V can be applied to the input pins with-
out regard to the supply voltage. This device can be used
to interface 5V to 3V systems and two supply systems such
as battery backup. This circuit prevents device destruction
due to mismatched supply and input voltages.
Features
s High Speed: fMAX = 175 MHz at VCC = 5V
s Low power dissipation: ICC = 4 µA (max) at TA = 25°C
s High noise immunity: VNIH = VNIL = 28% VCC (min)
s Power down protection provided on all inputs
s Low noise: VOLP = 0.8V (max)
s Pin and function compatible with 74HC164
Ordering Code:
Order Number Package Number
Package Description
74VHC164M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
74VHC164SJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC164MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC164N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
Description
A, B Data Inputs
CP Clock Pulse Input (Active Rising Edge)
MR Master Reset Input (Active LOW)
Q0–Q7
Outputs
© 1999 Fairchild Semiconductor Corporation DS011636.prf
www.fairchildsemi.com


74VHC164 데이터시트, 핀배열, 회로
Functional Description
The VHC164 is an edge-triggered 8-bit shift register with
serial data entry and an output from each of the eight
stages. Data is entered serially through one of two inputs
(A or B); either of these inputs can be used as an active
High Enable for data entry through the other input. An
unused input must be tied HIGH.
Each LOW-to-HIGH transition on the Clock (CP) input
shifts data one place to the right and enters into Q0 the log-
ical AND of the two data inputs (A • B) that existed before
the rising clock edge. A LOW level on the Master Reset
(MR) input overrides all other inputs and clears the register
asynchronously, forcing all Q outputs LOW.
Function Table
Operating
Inputs
Outputs
Mode
MR A B Q0 Q1–Q7
Reset (Clear)
L XX L
L–L
Shift
H L L L Q0–Q6
H L H L Q0–Q6
H H L L Q0–Q6
H H H H Q0–Q6
H = HIGH Voltage Levels
L = LOW Voltage Levels
X = Immaterial
Q = Lower case letters indicate the state of the referenced input or output
one setup time prior to the LOW-to-HIGH clock transition.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74VHC164 register

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