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MC14015BFEL 반도체 회로 부품 판매점

Dual 4-Bit Static Shift Register



ON Semiconductor 로고
ON Semiconductor
MC14015BFEL 데이터시트, 핀배열, 회로
MC14015B
Dual 4-Bit Static
Shift Register
The MC14015B dual 4–bit static shift register is constructed with
MOS P–channel and N–channel enhancement mode devices in a
single monolithic structure. It consists of two identical, independent
4–state serial–input/parallel–output registers. Each register has
independent Clock and Reset inputs with a single serial Data input.
The register states are type D master–slave flip–flops. Data is shifted
from one stage to the next during the positive–going clock transition.
Each register can be cleared when a high level is applied on the Reset
line. These complementary MOS shift registers find primary use in
buffer storage and serial–to–parallel conversion where low power
dissipation and/or noise immunity is desired.
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Logic Edge–Clocked Flip–Flop Design —
Logic state is retained indefinitely with clock level either high or low;
information is transferred to the output only on the positive going
edge of the clock pulse.
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range.
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol
Parameter
Value
VDD
Vin, Vout
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
– 0.5 to +18.0
– 0.5 to VDD + 0.5
Unit
V
V
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
± 10 mA
PD Power Dissipation,
per Package (Note 3.)
500 mW
TA Ambient Temperature Range
Tstg Storage Temperature Range
TL Lead Temperature
(8–Second Soldering)
– 55 to +125
– 65 to +150
260
°C
°C
°C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
v vhigh–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
PDIP–16
P SUFFIX
CASE 648
MARKING
DIAGRAMS
16
MC14015BCP
AWLYYWW
1
SOIC–16
D SUFFIX
CASE 751B
16
14015B
AWLYWW
1
TSSOP–16
DT SUFFIX
CASE 948F
16
14
015B
ALYW
SOEIAJ–16
F SUFFIX
CASE 966
1
16
MC14015B
AWLYWW
1
A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC14015BCP
PDIP–16
2000/Box
MC14015BD
SOIC–16
48/Rail
MC14015BDR2 SOIC–16 2500/Tape & Reel
MC14015BDT
TSSOP–16 2000/Tape & Reel
MC14015BF
SOEIAJ–16 See Note 1.
MC14015BFEL SOEIAJ–16 See Note 1.
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
© Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 3
1
Publication Order Number:
MC14015B/D


MC14015BFEL 데이터시트, 핀배열, 회로
MC14015B
TRUTH TABLE
CDR
Q0
00
0
10
1
X 0 No Change
XX1
0
X = Don’t Care
Qn = Q0, Q1, Q2, or Q3, as applicable.
Qn–1 = Output of prior stage.
Qn
Qn–1
Qn–1
No Change
0
PIN ASSIGNMENT
CB 1
Q3B 2
Q2A 3
Q1A 4
Q0A 5
RA 6
DA 7
VSS 8
16 VDD
15 DB
14 RB
13 Q0B
12 Q1B
11 Q2B
10 Q3A
9 CA
BLOCK DIAGRAM
Q0
7D
Q1
Q2
9C
R Q3
5
4
3
10
6
Q0
15 D
Q1
13
12
Q2
1C
R Q3
11
2
14
VDD = PIN 16
VSS = PIN 8
http://onsemi.com
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MC14015BFEL register

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MC14015BFEL

Dual 4-Bit Static Shift Register - ON Semiconductor