|
Philips |
www.DataSheet4U.com
TDA10023HT
Single chip DVB-C/MCNS channel receiver
Rev. 01 — 12 April 2005
Product data sheet
1. General description
The TDA10023HT is a single chip DVB-C/MCNS channel receiver for 4, 16, 32, 64, 128
and 256-QAM modulated signals. The device interfaces directly to the IF signal, which is
sampled by a 10-bit A/D converter.
The TDA10023HT performs the clock and the carrier recovery functions. The digital loop
filters for both clock and carrier recovery are programmable in order to optimize their
characteristics according to the current application.
After baseband conversion, equalization filters are used for echo cancellation in cable
applications. These filters are configured as T-spaced transversal equalizer or DFE
equalizer, so that the system performance can be optimized according to the network
characteristics. A proprietary equalization algorithm, independent of carrier offset, is
achieved in order to assist carrier recovery. Then a decision directed algorithm takes
place, to achieve final equalization convergence.
The TDA10023HT chip implements two FEC decoders, one for each standard. In the
DVB-C mode the TDA10023HT implements a Forney convolutional de-interleaver of depth
12 blocks and a Reed-Solomon decoder which corrects up to 8 erroneous bytes. The
de-interleaver and the Reed-Solomon decoder are automatically synchronized thanks to
the frame synchronization algorithm that uses the MPEG2 sync byte. Finally descrambling
according to DVB-C standard is achieved at the Reed-Solomon output. In the MCNS
mode the receiver error correction implements a soft decision trellis decoder to correct
random channel errors, a randomizer, a convolutional de-interleaver of depth I = 128, 64,
32, 16, 8 and J = 1, 2, 3, 4, 8, 16 for burst protection, and a Reed-Solomon decoder which
corrects up to 3 erroneous symbols. The de-interleaver and the Reed-Solomon decoder
are automatically synchronized using the frame sync trailer.
This device is controlled via an I2C-bus.
Philips Semiconductors
www.DataSheet4U.com
TDA10023HT
Single chip DVB-C/MCNS channel receiver
2. Features
s 4,16, 32, 64, 128 and 256 QAM demodulator (ITU-T J.83 annex A-B and C compatible)
s High performance for 256 QAM especially for direct IF applications
s On-chip 10-bit ADC
s On-chip PLL for crystal frequency multiplication (typically 16 MHz crystal)
s Digital down conversion
s Programmable half Nyquist filter (roll off = 0.12, 0.13, 0.15 and 0.18)
s Two PWM AGC outputs with programmable take-over point (for tuner and down
converter control)
s Clock timing recovery, with programmable second order loop filter
s Variable symbol rate capability from SACLK/64 to SACLK/4 (with low sampling clock:
SACLK = 36 MHz maximum) or from SACLK/128 to SACLK/8 (with high sampling
clock: SACLK = 72 MHz maximum)
s Programmable anti-aliasing filters
s Full digital carrier recovery loop
s Carrier acquisition range up to 9 % of symbol rate
s Integrated adaptive equalizer (linear transversal equalizer or decision feedback
equalizer)
s DVB compatible differential decoding and mapping
s On chip DVB-C full compliant FEC decoder (de-interleaver, Reed-Solomon decoder
and de-scrambler)
s On chip MCNS full compliant FEC decoder (trellis demodulator, de-randomizer,
de-interleaver and Reed-Solomon decoder)
s Multiple TS JQAM filter
s Parallel and serial transport stream interface simultaneously
s I2C-bus interface, for easy control
3. Applications
s Cable set-top boxes
s Cable modems
s Cable Network Interface Modules (NIMs)
s Multichannel Multipoint Distribution Service (MMDS) (ETS 300-749) set-top boxes
9397 750 14559
Product data sheet
Rev. 01 — 12 April 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
2 of 20
|