파트넘버.co.kr FIN1018 데이터시트 PDF


FIN1018 반도체 회로 부품 판매점

3.3V LVDS 1-Bit High Speed Differential Receiver



Fairchild Semiconductor 로고
Fairchild Semiconductor
FIN1018 데이터시트, 핀배열, 회로
March 2001
Revised April 2002
FIN1018
3.3V LVDS 1-Bit High Speed Differential Receiver
General Description
This single receiver is designed for high speed intercon-
nects utilizing Low Voltage Differential Signaling (LVDS)
technology. The receiver translates LVDS levels, with a typ-
ical differential input threshold of 100 mV, to LVTTL signal
levels. LVDS provides low EMI at ultra low power dissipa-
tion even at high frequencies. This device is ideal for high
speed transfer of clock or data.
The FIN1018 can be paired with its companion driver, the
FIN1017, or with any other LVDS driver.
Features
s Greater than 400Mbs data rate
s 3.3V power supply operation
s 0.4ns maximum pulse skew
s 2.5ns maximum propagation delay
s Low power dissipation
s Power-Off protection
s Fail safe protection for open-circuit, shorted and termi-
nated conditions
s Meets or exceeds the TIA/EIA-644 LVDS standard
s Flow-through pinout simplifies PCB layout
s 8-Lead SOIC and US-8 packages save space
Ordering Code:
Order Number
FIN1018M
FIN1018MX
FIN1018K8X
Package Number
Package Description
M08A
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
[TUBE]
M08A
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
[TAPE and REEL]
MAB08A
8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide
[TAPE and REEL]
Pin Descriptions
Pin Name
ROUT
RIN+
RIN
VCC
GND
NC
Description
LVTTL Data Output
Non-inverting Driver Input
Inverting Driver Input
Power Supply
Ground
No Connect
Connection Diagrams
8-Lead SOIC
Function Table
Input
RIN+
RIN
LH
HL
Fail Safe Condition
H = HIGH Logic Level
L = LOW Logic Level
Fail Safe = Open, Shorted, Terminated
Outputs
ROUT
L
H
H
Pin Assignment for US-8 Package
TOP VIEW
© 2002 Fairchild Semiconductor Corporation DS500502
www.fairchildsemi.com


FIN1018 데이터시트, 핀배열, 회로
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC)
DC Input Voltage (RIN+, RIN)
DC Output Voltage (DOUT)
DC Output Current (IO)
Storage Temperature Range (TSTG)
Max Junction Temperature (TJ)
Lead Temperature (TL)
(Soldering, 10 seconds)
ESD (Human Body Model)
ESD (Bus Pins RIN/RIN+ to GND)
ESD (Machine Model)
0.5V to +4.6V
0.5V to +4.7V
0.5V to +6V
16 mA
65°C to +150°C
150°C
260°C
6500V
9500V
300V
Recommended Operating
Conditions
Supply Voltage (VCC)
Input Voltage (VIN)
Magnitude of Differential Voltage
(|VID|)
Common-mode Input Voltage (VIC)
Operating Temperature (TA)
3.0V to 3.6V
0 to VCC
100mV to VCC
0.05V to 2.35V
40°C to +85°C
Note 1: The “Absolute Maximum Ratings”: are those values beyond which
damage to the device may occur. The databook specifications should be
met, without exception, to ensure that the system design is reliable over its
power supply, temperature and output/input loading variables. Fairchild
does not recommend operation of circuits outside databook specification.
DC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Symbol
Parameter
Test Conditions
Min
VTH Differential Input Threshold HIGH See Figure 1 and Table 1
VTL Differential Input Threshold LOW See Figure 1 and Table 1
IIN Input Current
VIN = 0V or VCC
II(OFF)
Power-OFF Input Current
VCC = 0V, VIN = 0V or 3.6V
VOH Output HIGH Voltage
IOH = −100 µA
IOH = −8 mA
VOL Output LOW Voltage
IOH = 100 µA
IOL = 8 mA
VIK Input Clamp Voltage
IIK = −18 mA
ICC Power Supply Current
Inputs Open, (RIN+ = 1V and RIN= 1.4V),
or (RIN+ = 1.4V and RIN= 1V)
CIN Input Capacitance
COUT
Output Capacitance
Note 2: All typical values are at TA = 25°C and with VCC = 3.3V.
100
VCC 0.2
2.4
1.5
Typ
(Note 2)
4
6
Max
100
±20
±20
0.2
0.5
7
Units
mV
mV
µA
µA
V
V
V
V
V
mA
pF
pF
AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Symbol
Parameter
Test Conditions
Min Typ Max
(Note 3)
Units
tPLH Propagation Delay LOW-to-HIGH
0.9 2.5 ns
tPHL Propagation Delay HIGH-to-LOW
0.9 2.5 ns
tTLH Output Rise Time (20% to 80%)
|VID| = 400 mV, CL = 10 pF
0.5 ns
tTHL Output Fall Time (80% to 20%)
See Figure 1 and Figure 2
0.5 ns
tSK(P)
Pulse Skew |tPLH - tPHL|
0.4 ns
tSK(PP)
Part-to-Part Skew (Note 4)
1.0 ns
Note 3: All typical values are at TA = 25°C and with VCC = 3.3V.
Note 4: tSK(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction
(either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits.
www.fairchildsemi.com
2




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FIN1018 receiver

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