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PDF HI-3282 Data sheet ( Hoja de datos )
| Número de pieza | HI-3282 | |
| Descripción | Serial Transmitter and Dual Receiver | |
| Fabricantes | HOLTIC | |
| Logotipo |  |
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July 2013
HI-3282, HI-3282B
ARINC 429
Serial Transmitter and Dual Receiver
GENERAL DESCRIPTION
The HI-3282 is a silicon gate CMOS device for interfacing
the ARINC 429 serial data bus to a 16-bit parallel data bus.
Two receivers and an independent transmitter are
provided. The receiver input circuitry and logic are
designed to meet the ARINC 429 specifications for loading,
level detection, timing, and protocol. The ARINC inputs of
the HI-3282-10 configurations also have internal lightning
protection to DO-160D, Level 3. The transmitter section
provides the ARINC 429 communication protocol. An
external ARINC 429 Line Driver such as the Holt HI-3182 or
HI-8585 is required to translate the 5 volt logic outputs to
ARINC 429 drive levels.
The 16-bit parallel data bus exchanges the 32-bit ARINC
data word in two steps when either loading the transmitter
or interrogating the receivers. The data bus interfaces with
CMOS and TTL.
Timing of all the circuitry begins with the master clock input,
CLK. For ARINC 429 applications, the master clock
frequency is 1 MHz.
Each independent receiver monitors the data stream with a
sampling rate 10 times the data rate. The sampling rate is
software selectable at either 1MHz or 125KHz. The results
of a parity check are available as the 32nd ARINC bit.
The transmitter has a First In, First Out (FIFO) memory to
store 8 ARINC words for transmission. The data rate of the
transmitter is software selectable by dividing the master
clock, CLK, by either 10 or 80. The master clock is used to
set the timing of the ARINC transmission within the required
resolution.
The HI-3282BPJx product has a minimum low speed data
rate of 6.5K BPS.
APPLICATIONS
• Avionics data communication
• Serial to parallel conversion
• Parallel to serial conversion
FEATURES
• ARINC specification 429 compatible
• Compatible with Industry-standard alternate
parts
• Small footprint 44-pin PQFP package option
• 16-Bit parallel data bus
• Direct receiver interface to ARINC bus
• Internal Lightning Protection of ARINC inputs
per DO-160D, Level 3 in -10 configurations
• Timing control 10 times the data rate
• Selectable data clocks
• Automatic transmitter data timing
• Self test mode
• Parity functions
• Low power, single 5 volt supply
• Industrial & extended temperature ranges
PIN CONFIGURATION (Top View)
N/C - 1
D/R1 - 2
D/R2 - 3
SEL - 4
EN1 - 5
EN2 - 6
BD15 - 7
BD14 - 8
BD13 - 9
BD12 - 10
BD11 - 11
HI-3282PQI
HI-3282PQI-10
HI-3282PQT
&
HI-3282PQT-10
33 - N/C
32 - N/C
31 - CWSTRX
30 - ENTX
29 - 429DO
28 -429DO
27 - TX/R
26 - PL2
25 - PL1
24 - BD00
23 - BD01
44-Pin Plastic Quad Flat Pack (PQFP)
(See page 10 for additional pin configurations)
(DS3282 Rev. O)
HOLT INTEGRATED CIRCUITS
www.holtic.com
07/13
1 page  
HI-3282, HI-3282B
FUNCTIONAL DESCRIPTION (cont.)
TRANSMITTER
A block diagram of the transmitter section is shown in Figure 3.
FIFO OPERATION
The FIFO is loaded sequentially by first pulsing PL1 to load byte 1
and then PL2 to load byte 2. The control logic automatically loads
the 31 bit word in the next available position of the FIFO. If TX/R,
the transmitter ready flag, is high (FIFO empty), then 8 words,
each 31 bits long, may be loaded. If TX/R is low, then only the
available positions may be loaded. If all 8 positions are full, the
FIFO ignores further attempts to load data.
DATA TRANSMISSION
When ENTX goes high, enabling transmission, the FIFO
positions are incremented with the top register loading into the
data transmission shift register. Within 2.5 data clocks the first
data bit appears at either 429DO or 429DO. The 31 bits in the
data transmission shift register are presented sequentially to the
outputs in the ARINC 429 format with the following timing:
ARINC DATA BIT TIME
DATA BIT TIME
NULL BIT TIME
WORD GAP TIME
HIGH SPEED
10 Clocks
5 Clocks
5 Clocks
40 Clocks
LOW SPEED
80 Clocks
40 Clocks
40 Clocks
320 Clocks
The word counter detects when all loaded positions are
transmitted and sets the transmitter ready flag, TX/R, high.
TRANSMITTER PARITY
Control register bit BD04 (PAREN) enables parity bit insertion into
transmitter data bit 32. Parity is always inserted if DBCEN is open
or high. If DBCEN is low, logic 0 on PAREN inserts data on bit 32,
and logic 1 on PAREN inserts parity on bit 32.
The parity generator counts the ONES in the 31-bit word. If the BD12
control word bit is set low, the 32nd bit transmitted will make parity
odd. If the control bit is high, the parity is even.
SELF TEST
If the BD05 control word bit is set low, 429DO or 429DO are internally
connected to the receivers inputs, bypassing the interface circuitry.
Data to Receiver 1 is as transmitted and data to Recevier 2 is the
complement. 429DO and 429DO outputs remain active during self
test.
SYSTEM OPERATION
The two receivers are independent of the transmitter. Therefore,
control of data exchanges is strictly at the option of the user. The only
restrictions are:
1. The received data may be overwritten if not retrieved within
one ARINC word cycle.
2. The FIFO can store 8 words maximum and ignores attempts
to load addition data if full.
3. Byte 1 of the transmitter data must be loaded first.
4. Either byte of the received data may be retrieved first. Both
bytes must be retrieved to clear the data ready flag.
5. After ENTX, transmission enable, goes high it cannot go low
until TX/R, transmitter ready flag, goes high. Otherwise, one
ARINC word is lost during transmission.
MASTER RESET (MR)
On a Master Reset data transmission and reception are immedi-
ately terminated, the transmit FIFO and receivers cleared as are
the transmit and receive flags. The Control Register is not affected
by a Master Reset.
DBCEN
CONTROL REGISTER BD04, BD12
BIT CLOCK
PARITY
GENERATOR
DATA AND
NULL TIMER
SEQUENCER
429DO
429DO
31 BIT PARALLEL
LOAD SHIFT REGISTER
WORD CLOCK
BIT
AND
WORD GAP
COUNTER
8 X 31 FIFO
ADDRESS
LOAD
DATA
CLOCK
DATA BUS
FIGURE 3. TRANSMITTER BLOCK DIAGRAM
START
SEQUENCE
WORD COUNTER
AND
FIFO CONTROL
INCREMENT
WORD COUNT
FIFO
LOADING
SEQUENCER
DATA CLOCK
DIVIDER
CONTROL REGISTER
BIT BD13
HOLT INTEGRATED CIRCUITS
5
TX/R
ENTX
PL1
PL2
CLK
TX CLK
5 Page 
HI-3282, HI-3282B
ORDERING INFORMATION
HI - 3282 Cx x -xx (Ceramic)
PART
NUMBER
No dash number
-10 (See Note 1)
INPUT SERIES RESISTANCE
BUILT-IN REQUIRED EXTERNALLY
35K Ohm
0
25K Ohm
10K to 15K Ohm
PART
NUMBER
I
T
M
TEMPERATURE
RANGE
-40°C TO +85°C
-55°C TO +125°C
-55°C TO +125°C
FLOW
I
T
M
BURN
IN
No
No
Yes
LEAD
FINISH
Gold (Pb-free, RoHS compliant)
Gold (Pb-free, RoHS compliant)
Tin / Lead (Sn / Pb) Solder
PART
NUMBER
CD
CL
PACKAGE
DESCRIPTION
40 PIN CERAMIC SIDE BRAZED DIP (40C)
44 PIN CERAMIC LEADLESS CHIP CARRIER (44S)
HI - 3282 x Px x x -xx (Plastic)
PART
NUMBER
No dash number
-10 (See Note 1)
INPUT SERIES RESISTANCE
BUILT-IN REQUIRED EXTERNALLY
35K Ohm
0
25K Ohm
10K to 15K Ohm
PART
NUMBER
Blank
F
PACKAGE
DESCRIPTION
Tin / Lead (Sn / Pb) Solder
100% Matte Tin (Pb-free RoHS compliant)
PART
NUMBER
I
T
M
TEMPERATURE
RANGE
-40°C TO +85°C
-55°C TO +125°C
-55°C TO +125°C
FLOW
I
T
M
BURN
IN
No
No
Yes
PART
NUMBER
PJ
PQ
PACKAGE
DESCRIPTION
44 PIN PLASTIC J-LEAD PLCC (44J)
44 PIN PLASTIC QUAD FLAT PACK (44PQS)
PART
NUMBER
Blank
B
MINIMUM
LOW SPEED DATA RATE
10.4 K BPS
6.5K BPS (PJ package only)
NOTES:
1. The -10 configuration requires an external 10K to 15K ohm resistor in series with each ARINC input to
guarantee specified voltage thresholds. The 15K ohm resistors are required to withstand DO-160F, Level 3,
Waveforms 3, 4 , 5A & 5B pin injection.
HOLT INTEGRATED CIRCUITS
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet HI-3282.PDF ] | |
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