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Cypress Semiconductor |
PRELIMINARY
CY14B116L/CY14B116N/CY14B116S
CY14E116L/CY14E116N/CY14E116S
16-Mbit (2048 K × 8/1024 K × 16/512 K × 32)
nvSRAM
Features
■ 16-Mbit nonvolatile static random access memory (nvSRAM)
❐ 25-ns, 30-ns and 45-ns access times
❐ Internally organized as 2048 K × 8 (CY14X116L),
1024 K × 16 (CY14X116N), 512 K × 32 (CY14X116S)
❐ Hands-off automatic STORE on power-down with only a
small capacitor
❐ STORE to QuantumTrap nonvolatile elements is initiated by
software, device pin, or AutoStore on power-down
❐ RECALL to SRAM initiated by software or power-up
■ High reliability
❐ Infinite read, write, and RECALL cycles
❐ 1 million STORE cycles to QuantumTrap
❐ Data retention: 20 years
■ Sleep mode operation
■ Low power consumption
❐ Active current of 75 mA at 45 ns
❐ Standby mode current of 650 A
❐ Sleep mode current of 10 A
■ Operating voltages:
❐ CY14B116X: VCC = 2.7 V to 3.6 V
❐ CY14E116X: VCC = 4.5 V to 5.5 V
■ Industrial temperature: –40 C to +85 C
■ Packages
❐ 44-pin thin small-outline package (TSOP II)
❐ 48-pin thin small-outline package (TSOP I)
❐ 54-pin thin small-outline package (TSOP II)
❐ 165-ball fine-pitch ball grid array (FBGA) package
■ Restriction of hazardous substances (RoHS) compliant
■ Offered speeds
❐ 44-pin TSOP II: 25 ns and 45 ns
❐ 48-pin TSOP I: 30 ns and 45 ns
❐ 54-pin TSOP II: 25 ns and 45 ns
❐ 165-ball FBGA: 25 ns and 45 ns
Functional Description
The C ypress CY14X1 16L/CY14X116N/CY14X116S i s a fast
SRAM, with a no nvolatile el ement in each memory cel l. T he
memory is organized as 2048 K bytes of 8 bits each or 1024 K
words of 16 bits each o r 512 K words of 32 bit s each . T he
embedded non volatile elemen ts inco rporate Qu antumTrap
technology, prod ucing the world’s mo st reli able nonvolatile
memory. The SRAM can be read and written an infinite number
of times. The nonvolatile d ata residin g in the nonvolatile
elements do not change when data is written to the SRAM. Data
transfers from th e SRAM to the nonvolatile e lements (the
STORE operation) takes place automatically at power-down. On
power-up, data is restored to the SRAM (the RECALL operation)
from th e non volatile me mory. Both th e ST ORE an d RECALL
operations are also available under software control.
Errata: The engineering samples do not meet the address hold after end of write (tHA) and static discharge voltage specifications. For information on silicon errata, see
Errata on page 33. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-67793 Rev. *G
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 1, 2014http://www.Datasheet4U.com
PRELIMINARY CY14B116L/CY14B116N/CY14B116S
CY14E116L/CY14E116N/CY14E116S
Logic Block Diagram[1, 2, 3]
A0-A11
QUANTUMTRAP
4096 X 4096
STORE
STATIC RAM
ARRAY
4096 X 4096
RECALL
VCC VCAP
POWER CONTROL
SLEEP MODE
CONTROL
ZZ
STORE / RECALL
CONTROL
HSB
SOFTWARE
DETECT
A2-A14
OE [4]
CE
WE
DQ 0-DQ 31
COLUMN IO
COLUMN DECODER
BA /BLE
BB /BHE
BC
BD
ZZ
A12-A20
Notes
1. Address A0 - A20 for ×8 configuration, address A0 - A19 for ×16 configuration and address A0 - A18 for ×32 configuration.
2. Data DQ0 - DQ7 for ×8 configuration, data DQ0 - DQ15 for ×16 configuration and data DQ0 - DQ31 for ×32 configuration.
3. BLE, BHE are applicable for ×16 configuration and BA, BB, BC, BD are applicable for ×32 configuration only.
4. TSOP II package is offered in single CE. TSOP I and BGA packages are offered in dual CE options. In this datasheet, for a dual CE device, CE refers to the internal
logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH.
Document #: 001-67793 Rev. *G
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