파트넘버.co.kr BH616UV4010 데이터시트 PDF


BH616UV4010 반도체 회로 부품 판매점

Ultra Low Power/High Speed CMOS SRAM 256K X 16 bit



Brilliance Semiconductor 로고
Brilliance Semiconductor
BH616UV4010 데이터시트, 핀배열, 회로
Ultra Low Power/High Speed CMOS SRAM
256K X 16 bit
Green package materials are compliant to RoHS
BH616UV4010
www.DataSheet4U.com
n FEATURES
Ÿ Wide VCC low operation voltage : 1.65V ~ 3.6V
Ÿ Ultra low power consumption :
VCC = 3.6V Operation current : 12mA (Max.) at 55ns
2mA (Max.) at 1MHz
Standby current : 2.0uA (Typ.) at 25OC
VCC = 1.2V Data retention current : 1.0uA at 25OC
Ÿ High speed access time :
-55 55ns (Max.) at VCC=1.65~3.6V
Ÿ Automatic power down when chip is deselected
Ÿ Easy expansion with CE1, CE2 and OE options
Ÿ I/O Configuration x8/x16 selectable by LB and UB pin.
Ÿ Three state outputs and TTL compatible
Ÿ Fully static operation, no clock, no refresh
Ÿ Data retention supply voltage as low as 1.0V
n DESCRIPTION
The BH616UV4010 is a high performance, ultra low power CMOS
Static Random Access Memory organized as 262,144 by 16 bits and
operates in a wide range of 1.65V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both
high speed and low power features with typical operating current of
1.5mA at 1MHz at 3.6V/25OC and maximum access time of 55ns at
1.65V/85OC.
Easy memory expansion is provided by an active LOW chip enable
(CE1), an active HIGH chip enable (CE2) and active LOW output
enable (OE) and three-state output drivers.
The BH616UV4010 has an automatic power down feature, reducing
the power consumption significantly when chip is deselected.
The BH616UV4010 is available in DICE form, JEDEC standard
48-pin TSOP-I and 48-ball BGA package.
n POWER CONSUMPTION
PRODUCT
FAMILY
OPERATING Icc STANDBY
TEMPERATURE
(ICCSB1, Max)
VCC=3.6V VCC=1.8V
BH616UV4010DI
BH616UV4010AI
Industrial
-25OC to +85OC
10uA
10uA
BH616UV4010TI
POWER DISSIPATION
1MHz
VCC=3.6V
10MHz
Icc Operating
(ICC, Max)
fMax.
1MHz
VCC=1.8V
10MHz
2mA 6mA 12mA 1.5mA 5mA
fMax.
8mA
PKG TYPE
DICE
BGA-48-0608
TSOP I-48
n PIN CONFIGURATIONS
n BLOCK DIAGRAM
A15 1
A14 2
A13 3
A12 4
A11 5
A10 6
A9 7
A8 8
NC 9
NC 10
WE 11
CE2 12
NC 13
UB 14
LB 15
NC 16
A17 17
A7 18
A6 19
A5 20
A4 21
A3 22
A2 23
A1 24
BH616UV4010TC
BH616UV4010TI
123456
A LB OE A0 A1 A2 NC
B DQ8 UB A3 A4 CE1 DQ0
C DQ9 DQ10 A5 A6 DQ1 DQ2
D VSS DQ11 A17 A7 DQ3 VCC
E VCC DQ12 NC A16 DQ4 VSS
48 A16
47 NC
46 VSS
45 DQ15
44 DQ7
43 DQ14
42 DQ6
41 DQ13
40 DQ5
39 DQ12
38 DQ4
37 VCC
36 DQ11
35 DQ3
34 DQ10
33 DQ2
32 DQ9
31 DQ1
30 DQ8
29 DQ0
28 OE
27 VSS
26 CE1
25 A0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
DQ0
.
.
.
.
.
.
DQ15
CE2
CE1
WE
OE
UB
LB
VCC
VSS
Address
Input
Buffer
10
. 16
.
.
. 16
.
.
Control
Row
Decoder
1024
Memory Array
1024 x 4096
Data
Input
Buffer
Data
Output
Buffer
16
16
4096
Column I/O
Write Driver
Sense Amp
256
Column Decoder
8
Address Input Buffer
A17 A15 A14 A13 A16 A2 A1 A0
F DQ14 DQ13 A14 A15 DQ5 DQ6
G DQ15 NC A12 A13 WE DQ7
H NC A8 A9 A10 A11 NC
48-ball BGA top view
Brilliance Semiconductor, Inc. reserves the right to change products and specifications without notice.
Detailed product characteristic test report is available upon request and being accepted.
R0201-BH616UV4010
1
Revision 1.0
Dec.
2005


BH616UV4010 데이터시트, 핀배열, 회로
n PIN DESCRIPTIONS
BH616UV4010
www.DataSheet4U.com
Name
A0-A17 Address Input
Function
These 18 address inputs select one of the 262,144 x 16 bit in the RAM
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
WE Write Enable Input
OE Output Enable Input
LB and UB Data Byte Control Input
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in standby power mode. The DQ pins will be in the high impedance
state when the device is deselected.
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impendence state when OE is inactive.
Lower byte and upper byte data input/output control pins.
DQ0-DQ15 Data Input/Output
Ports
VCC
VSS
16 bi-directional ports are used to read data from or write data into the RAM.
Power Supply
Ground
n TRUTH TABLE
MODE
CE1 CE2 WE OE LB UB
HXXXXX
Chip De-selected
(Power Down)
X
L
X
X
X
X
XXXXHH
LHHH L X
Output Disabled
LHHHX L
LL
Read
L HH L H L
LH
LL
Write
L H L XH L
LH
NOTES: H means VIH; L means VIL; X means dont care (Must be VIH or VIL state)
DQ0~DQ7 DQ8~DQ15 VCC CURRENT
High Z
High Z
ICCSB, ICCSB1
High Z
High Z
ICCSB, ICCSB1
High Z
High Z
ICCSB, ICCSB1
High Z
High Z
ICC
High Z
High Z
ICC
DOUT
DOUT
ICC
High Z
DOUT
ICC
DOUT
High Z
ICC
DIN DIN
ICC
X DIN
ICC
DIN X
ICC
R0201-BH616UV4010
2
Revision 1.0
Dec.
2005




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BH616UV4010 ram

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BH616UV4010

Ultra Low Power/High Speed CMOS SRAM 256K X 16 bit - Brilliance Semiconductor