|
|
Número de pieza | CY14B256L | |
Descripción | 256-Kbit (32K x 8) nvSRAM | |
Fabricantes | Cypress Semiconductor | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de CY14B256L (archivo pdf) en la parte inferior de esta página. Total 17 Páginas | ||
No Preview Available ! PRELIMINARY
CY14B256L
256-Kbit (32K x 8) nvSRAM
Features
• 25 ns, 35 ns, and 45 ns access times
• “Hands-off” automatic STORE on power down with only a
small capacitor
• STORE to QuantumTrap™ nonvolatile elements is initiated
by software, device pin, or AutoStore™ on power down
• RECALL to SRAM initiated by software or power up
• Infinite READ, WRITE, and RECALL cycles
• 10 mA typical ICC at 200 ns cycle time
• 200,000 STORE cycles to QuantumTrap
• 20-year data retention @ 55°C
• Single 3V operation with tolerance of +15%, –10%
• Commercial and industrial temperature
• SOIC and SSOP packages
• RoHS compliance
Logic Block Diagram
Functional Description
The Cypress CY14B256L is a fast static RAM with a nonvol-
atile element in each memory cell. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM provides
infinite read and write cycles while independent, nonvolatile
data resides in the highly reliable QuantumTrap cell. Data
transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power down.
On power up, data is restored to the SRAM (the RECALL
operation) from the nonvolatile memory. The STORE and
RECALL operations are also available under software control.
A5
A6
A7
A8
A9
A 11
A 12
A 13
www.DataShAee14t4U.com
QuantumTrap
512 X 512
STORE
STATIC RAM
ARRAY
512 X 512
RECALL
VCC
VCAP
POWER
CONTROL
STORE/
RECALL
CONTROL
HSB
SOFTWARE
DETECT
-A13 A0
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
COLUMN IO
COLUMN DEC
A0 A1 A2 A3 A4 A10
OE
CE
WE
Cypress Semiconductor Corporation
Document #: 001-06422 Rev. *E
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Revised January 27, 2007
[+] Feedback
1 page Table 1. Mode Selection
CE WE
HX
LH
LL
LH
LH
LH
LH
www.DataSheet4U.com
PRELIMINARY
CY14B256L
OE
A13 – A0
Mode
IO Power
X
X
Not Selected Output High-Z
Standby
L
X
Read SRAM
Output Data
Active
X
X
Write SRAM
Input Data
Active
L
0x0E38
Read SRAM
Output Data
Active[1, 2, 3]
0x31C7
Read SRAM
Output Data
0x03E0
Read SRAM
Output Data
0x3C1F
Read SRAM
Output Data
0x303F
Read SRAM
Output Data
0x03F8
AutoStore
Output Data
Disable
L
0x0E38
Read SRAM
Output Data
Active[1, 2, 3]
0x31C7
Read SRAM
Output Data
0x03E0
Read SRAM
Output Data
0x3C1F
Read SRAM
Output Data
0x303F
Read SRAM
Output Data
0x07F0
AutoStore
Output Data
Enable
L
0x0E38
Read SRAM
Output Data Active ICC2[1, 2, 3]
0x31C7
Read SRAM
Output Data
0x03E0
Read SRAM
Output Data
0x3C1F
Read SRAM
Output Data
0x303F
Read SRAM
Output Data
0x0FC0
Nonvolatile Store Output High-Z
L
0x0E38
Read SRAM
Output Data
Active[1, 2, 3]
0x31C7
Read SRAM
Output Data
0x03E0
Read SRAM
Output Data
0x3C1F
Read SRAM
Output Data
0x303F
Read SRAM
Output Data
0x0C63
Nonvolatile
Output High-Z
Recall
Notes
1. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
2. While there are 15 address lines on the CY14B256L, only the lower 14 lines are used to control software modes.
3. IO state depends on the state of OE. The IO table shown assumes OE low.
Document #: 001-06422 Rev. *E
Page 5 of 17
[+] Feedback
5 Page PRELIMINARY
Switching Waveforms
SRAM Read Cycle 1 (address controlled) [8, 9, 20]
CY14B256L
ADDRESS
DQ (DATA OUT)
tOHA
tAA
tRC
DATA VALID
SRAM Read Cycle 2 (CE controlled) [8, 20]
ADDRESS
CE
tRC
tLZCE
tACE
OE
DQ (DATA OUT)
www.DataSheet4U.com
ICC
tDOE
tLZOE
STANDBY
tPU
ACTIVE
tPD
tHZCE
tHZOE
DATA VALID
Note
20. HSB must remain HIGH during READ and WRITE cycles.
Document #: 001-06422 Rev. *E
Page 11 of 17
[+] Feedback
11 Page |
Páginas | Total 17 Páginas | |
PDF Descargar | [ Datasheet CY14B256L.PDF ] |
Número de pieza | Descripción | Fabricantes |
CY14B256I | 256-Kbit (32 K x 8) Serial (I2C) nvSRAM | Cypress Semiconductor |
CY14B256K | 256-Kbit (32K x 8) nvSRAM | Cypress Semiconductor |
CY14B256KA | 256 Kbit (32K x 8) nvSRAM | Cypress Semiconductor |
CY14B256L | 256-Kbit (32K x 8) nvSRAM | Cypress Semiconductor |
Número de pieza | Descripción | Fabricantes |
SLA6805M | High Voltage 3 phase Motor Driver IC. |
Sanken |
SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |