PDF CY14B101L Data sheet ( Hoja de datos )

Número de pieza	CY14B101L
Descripción	1-Mbit (128K x 8) nvSRAM
Fabricantes	Cypress Semiconductor
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No Preview Available ! PRELIMINARY CY14B101L 1-Mbit (128K x 8) nvSRAM Features • 25 ns, 35 ns, and 45 ns access times • “Hands-off” automatic STORE on power down with only a small capacitor • STORE to QuantumTrapTM nonvolatile elements is initiated by software, device pin, or AutostoreTM on power down www.DataSheet4•UR.cEoCmALL to SRAM initiated by software or power up • Infinite READ, WRITE, and RECALL cycles • 10 mA typical ICC at 200 ns cycle time • 200,000 STORE cycles to quantum trap • 20-year data retention @ 55°C • Single 3V operation +20%, –10% • Commercial and industrial temperature • SOIC and SSOP packages • RoHS compliance Logic Block Diagram Functional Description The Cypress CY14B101L is a fast static RAM with a nonvolatile element in each memory cell. The embedded nonvolatile elements incorporate QuantumTrap technology producing, the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles; while independent, nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power down. On power up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. Both the STORE and RECALL operations are also available under software control. QuantumTrap VCC VCAP 1024 x 1024 A5 POWER A6 STORE CONTROL A7 A8 A9 A 12 STATIC RAM ARRAY RECALL STORE/ RECALL CONTROL HSB A13 1024 X 1024 A 14 A 15 -A 16 SOFTWARE DETECT A15 A0 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 COLUMN IO COLUMN DEC A0 A1 A2 A3 A4 A10 A11 OE CE WE Cypress Semiconductor Corporation Document #: 001-06400 Rev. E • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised January 24, 2007 [+] Feedback 1 page Table 1. Mode Selection CE WE HX LH LL LH www.DataSheet4U.com L H LH LH PRELIMINARY CY14B101L OE A15 – A0 Mode IO Power X X Not Selected Output High-Z Standby L X Read SRAM Output Data Active X X Write SRAM Input Data Active L 0x4E38 Read SRAM Output Data Active[1, 2, 3] 0xB1C7 Read SRAM Output Data 0x83E0 Read SRAM Output Data 0x7C1F Read SRAM Output Data 0x703F Read SRAM Output Data 0x8B45 Autostore Output Data Disable L 0x4E38 Read SRAM Output Data Active[1, 2, 3] 0xB1C7 Read SRAM Output Data 0x83E0 Read SRAM Output Data 0x7C1F Read SRAM Output Data 0x703F Read SRAM Output Data 0x4B46 Autostore Output Data Enable L 0x4E38 Read SRAM Output Data Active ICC2[1, 2, 3] 0xB1C7 Read SRAM Output Data 0x83E0 Read SRAM Output Data 0x7C1F Read SRAM Output Data 0x703F Read SRAM Output Data 0x8FC0 Nonvolatile Output High-Z Store L 0x4E38 Read SRAM Output Data Active[1, 2, 3] 0xB1C7 Read SRAM Output Data 0x83E0 Read SRAM Output Data 0x7C1F Read SRAM Output Data 0x703F Read SRAM Output Data 0x4C63 Nonvolatile Output High-Z Recall Notes 1. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle. 2. While there are 17 address lines on the CY14B101L, only the lower 16 lines are used to control software modes. 3. IO state depends on the state of OE. The IO table shown is based on OE Low. Document #: 001-06400 Rev. E Page 5 of 18 [+] Feedback 5 Page PRELIMINARY Switching Waveforms SRAM Read Cycle 1(address controlled) [9, 10, 22] CY14B101L ADDRESS www.DataSheet4U.com DQ (DATA OUT) tOHA tAA SRAM Read Cycle 2 (CE and OE controlled) [9, 22] tRC DATA VALID ADDRESS CE OE DQ (DATA OUT) ICC tRC tLZCE tACE tDOE tLZOE STANDBY tPU ACTIVE tPD tHZCE tHZOE DATA VALID Note 22. HSB must remain HIGH during READ and WRITE cycles. Document #: 001-06400 Rev. *E Page 11 of 18 [+] Feedback 11 Page

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