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PDF N32T1630C1E Data sheet ( Hoja de datos )
| Número de pieza | N32T1630C1E | |
| Descripción | 32Mb Ultra-Low Power Asynchronous CMOS PSRAM | |
| Fabricantes | NanoAmp Solutions | |
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NanoAmp Solutions, Inc.
1982 Zanker Road, San Jose, CA 95112
ph: 408-573-8878, FAX: 408-573-8877
www.nanoamp.com
N32T1630C1E
32Mb Ultra-Low Power Asynchronous CMOS PSRAM
2M x 16 bit
Overview
The N32T1630C1E is an integrated memory
device containing a 32 Mbit Pseudo Static Random
Access Memory using a self-refresh DRAM array
organized as 2,097,152 words by 16 bits. It is
designed to be identical in operation and interface
to standard 6T SRAMS. The device is designed for
low standby and operating current and includes a
power-down feature to automatically enter standby
mode. Also included are several other power
saving modes: a deep sleep mode where data is
not retained in the array and partial array refresh
mode where data is retained in a portion of the
array. Both these modes reduce standby current
drain. The device can operate over a very wide
temperature range of -25oC to +85oC.
Features
• Dual voltage for Optimum Performance:
Vccq - 2.7V to 3.3V
Vcc - 2.7V to 3.3V
• Fast Cycle Times
TACC < 60 nS
TACC < 70 nS
• Very low standby current
ISB < 120µA
• Very low operating current
Icc < 25mA
• Dual rail operation
VCCQ and VSSQ for separate I/O power rail
• Compact Space Saving BGA Package
Product Family
Part Number
Package Operating
Type
Temperature
Power
Supply
N32T1630C1EZ 48-BGA -25oC to +85oC 2.7V - 3.3V(VCC)
Speed
60ns
70ns
Standby
Operating
Current (ISB), Current (Icc),
Max Max
120 µA 3 mA @ 1MHz
Figure 1: Pin Configuration
123456
A LB OE A0 A1 A2 ZZ
B I/O8 UB A3 A4 CE I/O0
C I/O9 I/O10 A5 A6 I/O1 I/O2
D VSSQ I/O11 A17 A7 I/O3 VCC
E VCCQ I/O12 NC A16 I/O4 VSS
F I/O14 I/O13 A14 A15 I/O5 I/O6
G I/O15 A19 A12 A13 WE I/O7
H A18 A8
A9 A10 A11 A20
48 Pin BGA (top)
6 x 8 mm
Table 1: Pin Descriptions
Pin Name
A0-A20
WE
CE
ZZ
OE
LB
UB
I/O0-I/O15
VCC
VSS
VCCQ
VSSQ
Pin Function
Address Inputs
Write Enable Input
Chip Enable Input
Deep Sleep Input
Output Enable Input
Lower Byte Enable Input
Upper Byte Enable Input
Data Inputs/Outputs
Power
Ground
Power I/O only
Ground I/O only
(DOC # 14-02-006 Rev C ECN 01-1040
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
1
1 page  
NanoAmp Solutions, Inc.
N32T1630C1E
Timings
Item
Read Cycle Time
Address Access Time
Page Mode Read Cycle Time
Page Mode Access Time
Chip Enable to Valid Output
Output Enable to Valid Output
Byte Select to Valid Output
Chip Enable to Low-Z output
Output Enable to Low-Z Output
Byte Select to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Byte Select Disable to High-Z Output
Output Hold from Address Change
Symbol
tRC
tAA
tPC
tPA
tCO
tOE
tLB, tUB
tLZ
tOLZ
tBZ
tHZ
tOHZ
tBHZ
tOH
-60
Min. Max.
60 20000
60
25 20000
25
60
25
60
10
5
10
05
05
05
5
-70
Min. Max.
70 20000
70
25 20000
25
70
25
70
10
5
10
05
05
05
5
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle Time
Page Mode Write Cycle Time
Chip Enable to End of Write
Address Valid to End of Write
Byte Select to End of Write
Write Pulse Width
Write Recovery Time
Write to High-Z Output
Address Setup Time
Data to Write Time Overlap
Data Hold from Write Time
End Write to Low-Z Output
tWC
tPWC
tCW
tAW
tBW
tWP
tWR
tWHZ
tAS
tDW
tDH
tOW
60 20000 70 20000
25 20000 25 20000
50 60
50 60
50 60
50 50
00
55
00
20 20
00
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Maximum Page Mode Cycle
Chip Enable High Pulse Width
tPGMAX
tCP
20000
20000
10 10
ns
ns
Do not access device with invalid cycle time (shorter than tRC, tWC) for a continous period > 20us.
(DOC # 14-02-006 Rev C ECN 01-1040
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
5
5 Page 
NanoAmp Solutions, Inc.
Variable Address Register
A20 - A5
A4
N32T1630C1E
A3 A2 A1 A0
Reserved for future
Preferably set to all 0
Array mode for ZZ
0 = PAR mode (default)
1 = RMS mode
ZZ Enable/Disable
1
1
0
0
0= DeepSleepEnabled
1 = Deep Sleep Disabled
(default)
Array half
0 = Bottom array (default)
1 = Top array
Array section
1 = 1/4 array
0 = 1/2 array
1 = Reserved
0 = Full array
(default)
Variable Address Register (VAR) Update Timings
A0-A4
CE
WE
ZZ
LB, UB
tAS
tZZWE
tWC
tAW
tWP
tBW
tWR
Deep Sleep Mode - Entry/Exit Timings
A4
CE
WE
LB, UB
ZZ
tAS
tZZWE
tWC
tAW
tWP
tBW
tWR
tZZMIN
tR
(DOC # 14-02-006 Rev C ECN 01-1040
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
11
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| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet N32T1630C1E.PDF ] | |
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