PDF WED2ZLRSP01S Data sheet ( Hoja de datos )

Número de pieza	WED2ZLRSP01S
Descripción	Dual Array Synchronous Pipeline Burst NBL SRAM
Fabricantes	White Electronic
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No Preview Available ! www.DataSheet4U.com White Electronic Designs WED2ZLRSP01S 512K x 32/256K x 32 Dual Array Synchronous Pipeline Burst NBL SRAM FEATURES Fast clock speed: 166, 150, 133, and 100MHz Fast access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns Fast OE# access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns Single +2.5V ± 5% power supply (VCC) Snooze Mode for reduced-standby power Individual Byte Write control Clock-controlled and registered addresses, data I/Os and control signals Burst control (interleaved or linear burst) Packaging: 209-bump BGA package Low capacitive bus loading DESCRIPTION The WED2ZLRSP01S, Dual Independent Array, NBL- SSRAM device employs high-speed, Low-Power CMOS silicon and is fabricated using an advanced CMOS process. WEDC’s 24Mb, Sync Burst SRAM MCP integrates two totally independent arrays, the ﬁrst organized as a 512K x 32, and the second a 256K x 32. All Synchronous inputs pass through registers controlled by a positive edge triggered, single clock input per array. The NBL or No Bus Latency Memory provides 100% bus utilizaton, with no loss of cycles caused by change in modal operation (Write to Read/Read to Write). All inputs except for Asynchronous Output Enable and Burst Mode control are synchronized on the positive or rising edge of Clock. Burst order control must be tied either HIGH or LOW, Write cycles are internally self-timed, and writes are initiated on the rising edge of clock. This feature eliminates the need for complex off-chip write pulse generation and proved increased timing ﬂexibility for incoming signals. PIN CONFIGURATION (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 A Vss A_DATb0 A_DATb1 A_DATb2 A_DATb3 Vss A_DATa0 A_DATa1 A_DATa2 A_DATa3 Vss B NC A_DATb4 A_DATb5 A_DATb6 A_DATb7 Vss A_DATa4 A_DATa5 A_DATa6 A_DATa7 NC C A_ADR A_ADR A_OE# A_ADV A_BWEb Vss A_BWEa A_ZZ A_ADR A_ADR A_ADR D A_ADR Vss A_CKE# Vcc Vcc Vcc Vcc Vcc Vcc A_ADR A_ADR E A_ADR A_CK A_GWE# Vcc Vcc Vcc Vcc Vcc Vcc A_ADR1 A_ADR0 F A_ADR Vss A_CS2# Vcc Vcc Vcc Vcc Vcc Vcc A_ADR A_ADR G A_ADR A_ADR A_CS1# A_CS2 A_BWEc Vss A_BWEd A_LBO# A_ADR A_ADR A_ADR H NC A_DATc0 A_DATc1 A_DATc2 A_DATc3 Vss A_DATd0 A_DATd1 A_DATd2 A_DATd3 NC J Vss A_DATc4 A_DATc5 A_DATc6 A_DATc7 Vss A_DATd4 A_DATd5 A_DATd6 A_DATd7 Vss K Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss L Vss B_DATb0 B_DATb1 B_DATb2 B_DAT3 Vss B_DATa0 B_DATa1 B_DATa2 B_DATa3 Vss M NC B_DATb4 B_DATb5 B_DATb6 B_DAT7 Vss B_DATa4 B_DATa5 B_DATa6 B_DATa7 NC N B_ADR B_ADR B_OE# B_ADV B_BWEb Vss B_BWEa B_ZZ B_ADR B_ADR B_ADR P B_ADR Vss B_CKE# Vcc Vcc Vcc Vcc Vcc Vcc B_ADR B_ADR R B_ADR B_CK B_GWE# Vcc Vcc Vcc Vcc Vcc Vcc B_ADR1 B_ADR0 T B_ADR Vss B_CS2# Vcc Vcc Vcc Vcc Vcc Vcc B_ADR B_ADR U B_ADR NC B_CS1# B_CS2 B_BWEc Vss B_BWEd B_LBO# B_ADR B_ADR B_ADR V NC B_DATc4 B_DATc5 B_DATc6 B_DATc7 Vss B_DATd4 B_DATd5 B_DATd6 B_DATd7 NC W Vss B_DATc0 B_DATc1 B_DATc2 B_DATc3 Vss B_DATd0 B_DATd1 B_DATd2 B_DATd3 Vss White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice. April, 2002 Rev. 0 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 1 page White Electronic Designs WED2ZLRSP01S ABSOLUTE MAXIMUM RATINGS* Voltage on Vdd Supply Relative to VSS VIN (DQx) VIN (Inputs) Storage Temperature (BGA) -0.3V to +3.6V -0.3V to +3.6V -0.3V to +3.6V -55°C to +125°C Short Circuit Output Current 100mA *Stress greater than those listed under “Absolute Maximum Ratings”: may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this speciﬁcation is not implied. Exposure to absolute maximum rating condtions for extended periods may affect reliability. ELECTRICAL CHARACTERISTICS (0°C ≤ TA ≤ 70°C) Description Symbol Conditions Input High (Logic 1) Voltage VIH Input Low (Logic 0) Voltage VIL Input Leakage Current ILI 0V ≤ VIN ≤ VCC Output Leakage Current ILO Output(s) Disabled, 0V ≤ VIN ≤ VCC Output High Voltage VOH IOH = -1.0mA Output Low Voltage VOL IOL = 1.0mA Supply Voltage VCC NOTES: 1. All voltages referenced to VSS (GND) 2. ZZ pin has an internal pull-up, and input leakage is higher. Min 1.7 -0.3 -5 -5 2.0 --- 2.375 Max VCC +0.3 0.7 5 5 --- 0.4 2.625 Units V V µA µA V V V Notes 1 1 2 1 1 1 DC CHARACTERISTICS Description Symbol Conditions Typ 166 150 MHz MHz 133 MHz 100 MHz Units Notes Power Supply Current: Operating IDD Device Selected; All Inputs ≤ VIL or ≥ VIH; Cycle Time = tCYC MIN; VCC = MAX; Output Open 650 600 560 500 mA 1, 2 Power Supply Current: Standby Device Deselected; VCC = MAX; All Inputs ≤ VSS + 0.2 ISB2 or VCC - 0.2; All Inputs Static; CK Frequency = 0; 30 60 60 60 60 mA 2 ZZ ≤ VIL Power Supply Current: Current Device Selected; All Inputs ≤ VIL or ≥ VIH; Cycle ISB3 Time =tCYC MIN; VCC = MAX; Output Open; ZZ ≥ VCC - 0.2V 20 40 40 40 40 mA 2 Clock Running Standby Current Device Deselected; VCC = MAX; All Inputs ISB4 ≤ VSS + 0.2 or VCC - 0.2; Cycle Time = tCYC MIN; ZZ ≤ VIL 140 120 100 80 mA 2 NOTES: 1. IDD is speciﬁed with no output current and increases with faster cycle times. IDD increases with faster cycle times and greater output loading. 2. Typical values are measured at 2.5V, 25°C, and 10ns cycle time. BGA CAPACITANCE Description Control Input Capacitance Input/Output Capacitance (DQ) Address Capacitance Clock Capacitance Symbol CI CO CA CCK Conditions TA = 25°C; f = 1MHZ TA = 25°C; f = 1MHZ TA = 25°C; f = 1MHZ TA = 25°C; f = 1MHZ Typ Max Units Notes 5 7 pF 1 6 8 pF 1 5 7 pF 1 3 5 pF 1 NOTES: 1. This parameter is sampled. White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice. April, 2002 Rev. 0 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 5 Page White Electronic Designs WED2ZLRSP01S FIG. 6 TIMING WAVEFORM OF CKE# OPERATION Clock CKE# tCES tCEH Address WRITE# A1 CEx# A2 A3 ADV OE# Data Out Data In tCD tLZC tHZC Q1 NOTES: WRITE# = L means WE# = L, and BWx# = L CEx# refers to the combination of CE1#, CE2 and CE2#. Note: Applies to both independent arrays. tCH tCL tCYC A4 A5 A6 tDS tDH D2 Q3 Q4 Dont Care Undefined White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice. April, 2002 Rev. 0 11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 11 Page

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