PDF WED2ZL361MS Data sheet ( Hoja de datos )

Número de pieza	WED2ZL361MS
Descripción	Synchronous Pipeline Burst NBL SRAM
Fabricantes	White Electronic
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No Preview Available ! www.DataSheet4U.com White Electronic Designs WED2ZL361MS 1Mx36 Synchronous Pipeline Burst NBL SRAM FEATURES  Fast clock speed: 250, 225, 200, 166, 150, 133MHz  Fast access times: 2.6, 2.8, 3.0, 3.5, 3.8, 4.2ns  Fast OE# access times: 2.6, 2.8, 3.0, 3.5, 3.8, 4.2ns  Separate +2.5V ± 5% power supplies for Core, I/O (VCC, VCCQ)  Snooze Mode for reduced-standby power  Individual Byte Write control  Clock-controlled and registered addresses, data I/Os and control signals  Burst control (interleaved or linear burst)  Packaging:  119-bump BGA package  Low capacitive bus loading DESCRIPTION The WEDC SyncBurst - SRAM family employs high-speed, low-power CMOS designs that are fabricated using an advanced CMOS process. WEDC’s 32Mb SyncBurst SRAMs integrate two 1M x 18 SRAMs into a single BGA package to provide 1M x 36 conﬁguration. All synchronous inputs pass through registers controlled by a positive- edge-triggered single-clock input (CK). The NBL or No Bus Latency Memory utilizes all the bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except output enable and linear burst order are synchronized to input clock. Burst order control must be tied “High or Low.” Asynchronous inputs include the sleep mode enable (ZZ). Output Enable controls the outputs at any given time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation and provides increased timing ﬂexibility for incoming signals. NOTE: NBL (No Bus Latency) is equivalent to ZBT™ PIN CONFIGURATION (TOP VIEW) 12 3 4 5 67 A VCCQ SA SA SA SA SA VCCQ B SA CE2 SA ADV# SA CE2# NC C NC SA SA VCC SA SA NC D DQc DQPc VSS NC VSS DQPb DQb E DQc DQc VSS CE1# VSS DQb DQb F VCCQ DQc VSS OE# VSS DQb VCCQ G DQc DQc BWc# SA BWb# DQb DQb H DQc DQc VSS WE# VSS DQb DQb J VCCQ VCC NC VCC NC VCC VCCQ K DQd DQd VSS CK VSS DQa DQa L DQd DQd BWd# NC BWa# DQa DQa M VCCQ DQd VSS CKE# VSS DQa VCCQ N DQd DQd VSS SA1 VSS DQa DQa P DQd DQPd VSS SA0 VSS DQPa DQa R NC SA LBO# VCC NC SA NC T NC NC SA SA SA NC ZZ U VCCQ NC NC NC NC NC VCCQ BLOCK DIAGRAM CK CKE# ADV# LBO# CE1# CE2 CE2# OE# WE# ZZ 1M x 18 CK CKE# ADV# LBO# CS1# CS2 CS2# OE# WE# ZZ 1M x 18 CK CKE# ADV# LBO# CS1# CS2 CS2# OE# WE# ZZ Address Bus (SA0 - SA19) DQc, DQd DQPc, DQPd DQa, DQb DQPa, DQPb DQa - DQd DQPa - DQPd White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice. Oct, 2002 Rev. 5 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 1 page White Electronic Designs WED2ZL361MS AC CHARACTERISTICS Parameter 250MHz 225MHz 200MHz 166MHz 150MHz 133MHz Symbol Units Min Max Min Max Min Max Min Max Min Max Min Max Clock Time tCYC 4.0 4.4 5.0 6.0 6.7 7.5 ns Clock Access Time tCD -- 2.6 -- 2.8 -- 3.0 -- 3.5 -- 3.8 -- 4.2 ns Output enable to Data Valid tOE -- 2.6 -- 2.8 -- 3.0 -- 3.5 -- 3.8 -- 4.2 ns Clock High to Output Low-Z tLZC 1.5 -- 1.5 -- 1.5 -- 1.5 -- 1.5 -- 1.5 -- ns Output Hold from Clock High tOH 1.5 -- 1.5 -- 1.5 -- 1.5 -- 1.5 -- 1.5 -- ns Output Enable Low to output Low-Z tLZOE 0.0 -- 0.0 -- 0.0 -- 0.0 -- 0.0 -- 0.0 -- ns Output Enable High to Output High-Z tHZOE -- 2.6 -- 2.8 -- 3.0 -- 3.0 -- 3.0 -- 3.5 ns Clock High to Output High-Z tHZC -- 2.6 -- 2.8 -- 3.0 -- 3.0 -- 3.0 -- 3.5 ns Clock High Pulse Width tCH 1.7 -- 2.0 -- 2.0 -- 2.2 -- 2.2 -- 2.2 -- ns Clock Low Pulse Width tCL 1.7 -- 2.0 -- 2.0 -- 2.2 -- 2.2 -- 2.2 -- ns Address Setup to Clock High tAS 1.2 -- 1.4 -- 1.4 -- 1.5 -- 1.5 -- 1.5 -- ns CKE Setup to Clock High tCES 1.2 -- 1.4 -- 1.4 -- 1.5 -- 1.5 -- 1.5 -- ns Data Setup to Clock High tDS 1.2 -- 1.4 -- 1.4 -- 1.5 -- 1.5 -- 1.5 -- ns Write Setup to Clock High tWS 1.2 -- 1.4 -- 1.4 -- 1.5 -- 1.5 -- 1.5 -- ns Address Advance to Clock High tADVS 1.2 -- 1.4 -- 1.4 -- 1.5 -- 1.5 -- 1.5 -- ns Chip Select Setup to Clock High tCSS 1.2 -- 1.4 -- 1.4 -- 1.5 -- 1.5 -- 1.5 -- ns Address Hold to Clock high tAH 0.3 -- 0.4 -- 0.4 -- 0.5 -- 0.5 -- 0.5 -- ns CKE Hold to Clock High tCEH 0.3 -- 0.4 -- 0.4 -- 0.5 -- 0.5 -- 0.5 -- ns Data Hold to Clock High tDH 0.3 -- 0.4 -- 0.4 -- 0.5 -- 0.5 -- 0.5 -- ns Write Hold to Clock High tWH 0.3 -- 0.4 -- 0.4 -- 0.5 -- 0.5 -- 0.5 -- ns Address Advance to Clock High tADVH 0.3 -- 0.4 -- 0.4 -- 0.5 -- 0.5 -- 0.5 -- ns Chip Select Hold to Clock High tCSH 0.3 -- 0.4 -- 0.4 -- 0.5 -- 0.5 -- 0.5 -- ns ZZ High to Power Down tPDS 2 -- 2 -- 2 -- 2 -- 2 -- 2 -- cycle ZZ Low to Power Up tPUS 2 -- 2 -- 2 -- 2 -- 2 -- 2 -- cycle NOTES: 1. All Address inputs must meet the speciﬁed setup and hold times for all rising clock (CK) edges when ADV is sampled low and CEx# is sampled valid. All other synchronous inputs must meet the speciﬁed setup and hold times whenever this device is chip selected. 2. Chip enable must be valid at each rising edge of CK (when ADV is Low) to remain enabled. 3. A write cycle is deﬁned by WE# low having been registered into the device at ADV Low. A Read cycle is deﬁned by WE# High with ADV Low. Both cases must meet setup and hold times. AC TEST CONDITIONS (0 ≤ TA ≤ 70°C, VCC = 2.5V ± 5%; Commercial or -40°C ≤ Ta ≤ 85°C; VCC = 2.5V ± 5%; Industrial) Parameter Input Pulse Level Input Rise and Fall Time (Measured at 20% to 80%) Input and Output Timing Reference Levels Output Load Value 0 to 2.5V 1.0V/ns 1.25V See Output Load (A) OUTPUT LOAD (A) Dout Zo=50Ω RL=50Ω 30pF* VL=1.25V OUTPUT LOAD (B) (for tLZC, tLZOE, tHZOE, and tHZC) +2.5V Dout 1667Ω 1538Ω 5pF* *Including Scope and Jig Capacitance White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice. Oct, 2002 Rev. 5 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 5 Page White Electronic Designs WED2ZL361MS FIG. 6 TIMING WAVEFORM OF CE# OPERATION Clock CKE# tCSS tCSH Address A1 A2 A3 A4 WRITE# CEx# ADV OE# Data Out Data In tLZtOOEE Q1 tHZC Q2 ttLCZDC tDS tDH D3 NOTES: WRITE# = L means WE# = L, and BWx# = L CEx# refers to the combination of CE1#, CE2 and CE2#. A5 Q4 tCH tCL tCYC D5 Dont Care Undefined White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice. Oct, 2002 Rev. 5 11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 11 Page

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