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PDF K7A403609B Data sheet ( Hoja de datos )
| Número de pieza | K7A403609B | |
| Descripción | 128Kx36/x32 & 256Kx18 Synchronous SRAM | |
| Fabricantes | Samsung semiconductor | |
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K7A403609A
K7A401809A
128Kx36 & 256Kx18 Synchronous SRAM
Document Title
128Kx36 & 256Kx18-Bit Synchronous Pipelined Burst SRAM
Revision History
Rev. No History
0.0 Initial draft
0.1 Add tCYC 300MHz.
0.2 1. Changed DC condition at Icc and ISB.
Icc ; from 540mA to 590mA at -30,
from 490mA to 540mA at -27,
from 440mA to 490mA at -25,
from 410mA to 460mA at -22,
from 390mA to 440mA at -20,
from 370mA to 420mA at -18,
ISB ; from 190mA to 200mA at -30,
from 180mA to 190mA at -27,
from 170mA to 180mA at -25,
from 160mA to 170mA at -22,
from 150mA to 160mA at -20,
from 140mA to 150mA at -18,
1.0 1. Final spec release
2. Changed input & output capacitance.
CIN ; from 6pF to 5pF,
COUT ; from 8pF to 7pF,
3.Changed part number
from K7A4036(18)00A -under 167MHz to K7A4036(18)09A -over183MHz
2.0 1. Changed Input setup at -275MHz and 300MHz
From 0.8ns to 0.75ns,
3.0 1. Changed Input setup at -300MHz
From 0.75ns to 0.6ns
Draft Date
Jan. 22. 2000
Feb. 10. 2000
April. 03. 2000
May. 15. 2000
August. 17. 2000
August. 30. 2000
Remark
Preliminary
Preliminary
Preliminary
Final
Final
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
- 1 - August 2000
Rev 3.0
1 page  
K7A403609A
K7A401809A
128Kx36 & 256Kx18 Synchronous SRAM
FUNCTION DESCRIPTION
The K7A403609A and K7A401809A are synchronous SRAM designed to support the burst address accessing sequence of the P6
and Power PC based microprocessor. All inputs (with the exception of OE, LBO and ZZ) are sampled on rising clock edges. The start
and duration of the burst access is controlled by ADSC, ADSP and ADV and chip select pins.
The accesses are enabled with the chip select signals and output enabled signals. Wait states are inserted into the access with
ADV.
When ZZ is pulled high, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ
returns to low, the SRAM normally operates after 2cycles of wake up time. ZZ pin is pulled down internally.
Read cycles are initiated with ADSP(regardless of WEx and ADSC)using the new external address clocked into the on-chip address
register whenever ADSP is sampled low, the chip selects are sampled active, and the output buffer is enabled with OE. In read oper-
ation the data of cell array accessed by the current address, registered in the Data-out registers by the positive edge of CLK, are car-
ried to the Data-out buffer by the next positive edge of CLK. The data, registered in the Data-out buffer, are projected to the output
pins. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on the subsequent clock edges. The address
increases internally for the next access of the burst when WEx are sampled High and ADV is sampled low. And ADSP is blocked to
control signals by disabling CS1.
All byte write is done by GW(regaedless of BW and WEx.), and each byte write is performed by the combination of BW and WEx
when GW is high.
Write cycles are performed by disabling the output buffers with OE and asserting WEx. WEx are ignored on the clock edge that sam-
ples ADSP low, but are sampled on the subsequent clock edges. The output buffers are disabled when WEx are sampled
Low(regardless of OE). Data is clocked into the data input register when WEx sampled Low. The address increases internally to the
next address of burst, if both WEx and ADV are sampled Low. Individual byte write cycles are performed by any one or more byte
write enable signals(WEa, WEb, WEc or WEd) sampled low. The WEa control DQa0 ~ DQa7 and DQPa, WEb controls DQb0 ~ DQb7
and DQPb, WEc controls DQc0 ~ DQc7 and DQPc, and WEd control DQd0 ~ DQd7 and DQPd. Read or write cycle may also be initi-
ated with ADSC, instead of ADSP. The differences between cycles initiated with ADSC and ADSP as are follows;
ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.
WEx are sampled on the same clock edge that sampled ADSC low(and ADSP high).
Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external
address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state
of the LBO pin. When this pin is Low, linear burst sequence is selected. When this pin is High, Interleaved burst sequence is
selected.
BURST SEQUENCE TABLE
LBO PIN
HIGH
First Address
Fourth Address
Case 1
A1 A0
00
01
10
11
Case 2
A1 A0
01
00
11
10
Case 3
A1 A0
10
11
00
01
(Interleaved Burst)
Case 4
A1 A0
11
10
01
00
Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.
BQ TABLE
LBO PIN
LOW
First Address
Fourth Address
Case 1
A1 A0
00
01
10
11
Case 2
A1 A0
01
10
11
00
Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.
Case 3
A1 A0
10
11
00
01
(Linear Burst)
Case 4
A1 A0
11
00
01
10
ASYNCHRONOUS TRUTH TABLE
(See Notes 1 and 2):
OPERATION
ZZ OE I/O STATUS
Sleep Mode
HX
High-Z
Read
LL
LH
DQ
High-Z
Write
L X Din, High-Z
Deselected
LX
High-Z
Notes
1. X means "Don′t Care".
2. ZZ pin is pulled down internally
3. For write cycles that following read cycles, the output buffers must be
disabled with OE, otherwise data bus contention will occur.
4. Sleep Mode means power down state of which stand-by current does
not depend on cycle time.
5. Deselected means power down state of which stand-by current
depends on cycle time.
- 5 - August 2000
Rev 3.0
5 Page 
K7A403609A
K7A401809A
128Kx36 & 256Kx18 Synchronous SRAM
- 11 -
August 2000
Rev 3.0
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet K7A403609B.PDF ] | |
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