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K7A401809B 반도체 회로 부품 판매점

128Kx36/x32 & 256Kx18 Synchronous SRAM



Samsung semiconductor 로고
Samsung semiconductor
K7A401809B 데이터시트, 핀배열, 회로
K7A403609A
K7A401809A
128Kx36 & 256Kx18 Synchronous SRAM
Document Title
128Kx36 & 256Kx18-Bit Synchronous Pipelined Burst SRAM
Revision History
Rev. No History
0.0 Initial draft
0.1 Add tCYC 300MHz.
0.2 1. Changed DC condition at Icc and ISB.
Icc ; from 540mA to 590mA at -30,
from 490mA to 540mA at -27,
from 440mA to 490mA at -25,
from 410mA to 460mA at -22,
from 390mA to 440mA at -20,
from 370mA to 420mA at -18,
ISB ; from 190mA to 200mA at -30,
from 180mA to 190mA at -27,
from 170mA to 180mA at -25,
from 160mA to 170mA at -22,
from 150mA to 160mA at -20,
from 140mA to 150mA at -18,
1.0 1. Final spec release
2. Changed input & output capacitance.
CIN ; from 6pF to 5pF,
COUT ; from 8pF to 7pF,
3.Changed part number
from K7A4036(18)00A -under 167MHz to K7A4036(18)09A -over183MHz
2.0 1. Changed Input setup at -275MHz and 300MHz
From 0.8ns to 0.75ns,
3.0 1. Changed Input setup at -300MHz
From 0.75ns to 0.6ns
Draft Date
Jan. 22. 2000
Feb. 10. 2000
April. 03. 2000
May. 15. 2000
August. 17. 2000
August. 30. 2000
Remark
Preliminary
Preliminary
Preliminary
Final
Final
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
- 1 - August 2000
Rev 3.0


K7A401809B 데이터시트, 핀배열, 회로
K7A403609A
K7A401809A
128Kx36 & 256Kx18 Synchronous SRAM
128Kx36 & 256Kx18-Bit Synchronous Pipelined Burst SRAM
FEATURES
• Synchronous Operation.
• 2 Stage Pipelined operation with 4 Burst.
• On-Chip Address Counter.
• Self-Timed Write Cycle.
• On-Chip Address and Control Registers.
• VDD= 3.3V+0.3V/-0.165V Power Supply.
• VDDQ Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O.
• 5V Tolerant Inputs Except I/O Pins.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• LBO Pin allows a choice of either a interleaved burst or a linear
burst.
• Three Chip Enables for simple depth expansion with No Data Cont-
nention ; 2cycle Enable, 1cycle Disable.
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• TTL-Level Three-State Output.
• 100-TQFP-1420A .
FAST ACCESS TIMES
PARAMETER
Symbol -30 -27 -25 -22 -20 -18 Unit
Cycle Time
tCYC 3.3 3.6 4.0 4.4 5.0 5.4 ns
Clock Access Time
tCD 2.2 2.2 2.4 2.6 2.8 3.0 ns
Output Enable Access Time tOE 2.2 2.2 2.4 2.6 2.8 3.0 ns
GENERAL DESCRIPTION
The K7A403609A and K7A401809A are 4,718,592-bit Syn-
chronous Static Random Access Memory designed for high
performance second level cache of Pentium and Power PC
based System.
It is organized as 128K(256K) words of 36(18) bits and inte-
grates address and control registers, a 2-bit burst address
counter and added some new functions for high perfor-
mance cache RAM applications; GW, BW, LBO, ZZ. Write
cycles are internally self-timed and synchronous.
Full bus-width write is done by GW, and each byte write is
performed by the combination of WEx and BW when GW is
high. And with CS1 high, ADSP is blocked to control signals.
Burst cycle can be initiated with either the address status
processor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated inter-
nally in the systems burst sequence and are controlled by
the burst address advance(ADV) input.
LBO pin is DC operated and determines burst sequence(lin-
ear or interleaved).
ZZ pin controls Power Down State and reduces Stand-by
current regardless of CLK.
The K7A403609A and K7A401809A are fabricated using
SAMSUNGs high performance CMOS technology and is
available in a 100pin TQFP package. Multiple power and
ground pins are utilized to minimize ground bounce.
LOGIC BLOCK DIAGRAM
CLK
LBO
ADV
ADSC
BURST CONTROL
LOGIC
BURST
ADDRESS A0~A1
COUNTER
128Kx36 , 256Kx18
MEMORY
ARRAY
ADSP
A0~A16
or A0~A17
A0~A1
ADDRESS
REGISTER
A2~A16
or A2~A17
CS1
CS2
CS2
GW
BW
WEx
(x=a,b,c,d or a,b)
CONTROL
LOGIC
OE
ZZ
DQa0 ~ DQd7 or DQa0 ~ DQb7
DQPa ~ DQPd
DQPa ~ DQPb
OUTPUT
REGISTER
BUFFER
36 or 18
DATA-IN
REGISTER
- 2 - August 2000
Rev 3.0




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